Synopsys introduced the HAPS-60 series of rapid prototyping systems—a comprehensive solution that eases complex SoC design and verification challenges. The HAPS-60 series, part of the Confirma(tm) Rapid Prototyping Platform, is an easy-to-use and cost-effective rapid prototyping system that enables early hardware/software co-verification and system-level integration at near-real-time run-rates, using at-speed, real-world interfaces.

Synopsys announced that eSilicon and Brite Semiconductor have joined the Synopsys IP OEM Partner Program along with renewed members Global Unichip and Open-Silicon. Through the IP OEM Partner Program, members standardise on Synopsys’ broad portfolio of silicon-proven DesignWare(r) interface and analogue IP such as USB, PCI Express(r), DDR, HDMI, SATA, Ethernet, MIPI IP including 3GDigRF, CSI-2, D-PHY, data converters and audio codecs for their ...

Synopsys, Inc. today announced availability of the DesignWare DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. These standards include LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), and DDR2. The DesignWare DDR multiPHY enables designers to target different DDR types for a single chip through simple software control. This capabili...

Synopsys announced that its DesignWare SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification. To achieve certification, the IP must pass protocol, electrical, and interoperability tests for SuperSpeed USB (USB 3.0, 5 Gbps) and Hi-Speed USB (USB 2.0, 480 Mbps). Synopsys created a fully integrated USB 3.0 IP solution, optimising all speed modes into a ...

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and SiliconBlue, a leader in ultra-low power, single-chip SRAM FPGAs, today announced that SiliconBlue has chosen Synopsys Synplify Pro FPGA synthesis software as the synthesis tool of choice for its iCE65 family of mobileFPGA(tm) devices. SiliconBlue will distribute with its iCEcube software a version of the Synplify Pro so...

Synopsys announced that the Galaxy Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve first-pass silicon success of the 40-nanometer (nm) baseband processor for its X-GOLD(tm) 626 3G wireless analogue and digital system-in-package (SIP). Infineon utilised the Galaxy platform's powerful implementation flow to optimise the chip's multiple functional modes with multi-corner/multi-mode (MCMM) technology, taking advantage...

Synopsys announced that Nationz Technologies, Inc. has successfully achieved first-pass silicon success of a 2.5-gigahertz (GHz), 126-channel RF transceiver system-on-chip (SoC) design by using Synopsys' CustomSim™ mixed-signal and VCS® functional verification solutions, part of Synopsys' Discovery™ Verification Platform. These Synopsys tools delivered accurate and high-performance transient analysis of the power-up operation to within five ...

Synopsys, Inc. announced it has completed its acquisition of CoWare, Inc., a global supplier of software and services for electronic systems design.

Synopsys announced that Renesas Technology Corp., the world's No. 1 supplier of microcontrollers and one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys Proteus optical proximity correction (OPC) for 28-nanometer (nm) development. The 28-nm node pushes the limits for single-exposure photon-based lithography, and by selecting Proteus, Renesas can achieve ...

Synopsys introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimise iterations to speed up physical implementation. To address these challenges, topographical technology in Design...

Synopsys announced that it has enhanced its Galaxy Custom Designer solution with the addition of SmartDRD, an innovative design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analogue and custom designs. SmartDRD automates many DRC repair tasks, reducing hours of manual effort to mere seconds.

Synopsys and the Belgian nanoelectronics research center, imec, today announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterising and optimising the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.

Synopsys announced that Yamaha, a leading provider of mobile audio and Graphics LSI chip products, achieved their aggressive performance targets ahead of schedule with Design Compiler(R) Graphical and successfully taped out their latest Graphics LSI chip.

Synopsys announced that APAC IC Layout Consultant, Inc., a global provider of IC physical design services, has adopted Synopsys’ Galaxy Custom Designer implementation solution. APAC IC, based in the Philippines, benefited from the ease with which Galaxy Custom Designer can be adopted to quickly achieve high productivity for its team of layout engineers servicing a worldwide customer base.

Synopsys announced that Aeroflex Colorado Springs, Inc., a global provider of high-technology solutions to the aerospace, defense and broadband communications markets, has successfully deployed Synopsys’ CustomSim unified circuit simulation solution for the development and verification of its high reliability integrated circuits (ICs). The CustomSim solution delivers performance improvements of up to 60x over SPICE, increasing designer producti...

Synopsys announced the addition of silicon-proven DesignWare MIPI IP consisting of 3G DigRF Controllers and PHY, Camera Serial Interface 2 (CSI-2) Host Controller and D-PHY to its IP portfolio. The Mobile Industry Processor Interface (MIPI) Alliance defines a set of standard hardware interfaces between mobile baseband processors, RF integrated circuits (ICs) and peripherals typically found in smartphones and multimedia handheld devices.

Synopsys announced the availability of high quality DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. With full support for new features of the HDMI 1.4 specification including HEAC, 3D formats, real-time content signaling, 4K x 2K resolution and 10.2 Gbps aggregate bandwidth, the DesignWare HDMI IP enables design...

Synopsys announced the DesignWare USB 3.0 Protocol Analyzer, a new graphical debugger for SuperSpeed USB 3.0, the latest generation of the USB interface that delivers 10 times the speed of Hi-Speed USB 2.0. The DesignWare USB 3.0 Protocol Analyzer simplifies debug for engineers verifying SuperSpeed USB 3.0 and USB 2.0 interfaces in their systems-on-chip (SoCs) by providing a graphical view of the protocol traffic. It helps users quickly identify...

Synopsys announced the availability of SuperSpeed USB 3.0 transaction-level models (TLM) supporting the Open SystemC Initiative (OSCI) TLM-2.0 API specification. The models are TLM representations of the Synopsys DesignWare(r) SuperSpeed USB 3.0 Device and xHCI Host Controller IP. The SuperSpeed USB 3.0 models enable pre-RTL and pre-silicon software development, verification and architecture exploration. They are part of the DesignWare System-Lev...

Synopsys announced the immediate availability of PrimeTime 2009.12, delivering up to 2X speed up of timing signoff through the addition of threaded multicore processing. With this latest addition, Synopsys’ PrimeTime tool provides a new level of flexibility enabling design teams to achieve optimal runtime performance across their heterogeneous multicore compute environments by utilising distributed and threaded multicore processing in tandem. ...