Synopsys announced that Open-Silicon, a leading system-on-chip (SoC) design and semiconductor manufacturing company, has licensed and integrated 50 high-speed DesignWare® IP products into customers' chips with 100 percent first-pass silicon success. The IP products include complete solutions consisting of configurable digital controllers, PHYs which support leading process technologies from 180 to 28 nanometers, verification IP, as well as analo...

Synopsys announced today that the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has been awarded Synopsys' Tenth annual Tenzing Norgay Interoperability Achievement Award for providing a platform for driving market acceptance, adoption and implementation of standardized technologies. IEEE-ISTO has provided an operational infrastructure to the global technology community for the development, adoption and certification of industry ...

Synopsys announced that Samsung Electronics' Foundry business (Samsung Foundry) has successfully taped out its first 32-nanometer (nm) system-on-chip (SoC) design using Synopsys' Galaxy™ Implementation Platform. Samsung Foundry selected the Galaxy Implementation Platform as one of its implementation solutions for its mobile application processor because the platform's seamless integration enabled them to meet timing while minimizing power consu...

Synopsys unveiled new PrimeTime HyperScale technology that enables static timing analysis (STA) to scale beyond 500 million instances. PrimeTime HyperScale technology provides design engineers the insight required to solve many of the timing integration and closure problems they face with today’s large system-on-chip (SoC) design flows while delivering a 5 to 10X boost in performance and capacity.

Synopsys announced it is delivering an optimized, pre-validated design environment for the Common Platform alliance (CPA) 32/28-nanometer(nm) high-k metal gate (HKMG) technology based on Synopsys' Lynx Design System.

Synopsys introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and implementation of complex system-on-chips (SoCs). Today's SoCs require libraries that contain hundreds of gigabytes of timing, power, noise and process variation data to ensure the chip meets all performance criteria. The Galaxy Characterizati...

Synopsys unveiled Rapid3D technology, a new 3D fast field solver engine fully integrated into Synopsys' StarRC™ Custom parasitic extraction solution. Building on the gold standard Raphael NXT engine, Rapid3D technology delivers attofarad accuracy and significant speedup by incorporating the latest advancements in 3D field solver algorithms. These algorithms take full advantage of modern multicore hardware to solve the accuracy and runtime chal...

Synopsys announced it has acquired technology, engineering resources and other assets of Synfora, Inc., a provider of C/C++ high-level synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. The asset acquisition strengthens Synopsys' position in system-level design and verification and enhances the company's FPGA-based prototyping solutions.

Synopsys announced that it has collaborated with TSMC to validate Synopsys’ custom design solution with TSMC’s 28-nanometer (nm) interoperable process design kit (iPDK) and Analog/Mixed-Signal (AMS) Reference Flow 1.0. TSMC’s 28nm reference phase-locked loop (PLL) design was used to validate Synopsys’ comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0. The validated sol...

Synopsys announced that it is delivering comprehensive design enablement for TSMC’s 28 nanometer (nm) process technology with TSMC Reference Flow 11.0. New features of the flow include solutions for system-level design and verification, added capabilities for 28-nm design, including In-Design physical verification, and support for thru-silicon via (TSV) technology for 3D IC design. Through Reference Flow 11.0, Synopsys tools and IP enable enhan...

Synopsys, Inc. today announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the indust...

Synopsys, Inc. today announced that its Synphony HLS (High Level Synthesis) product now includes optimized support for Xilinx Virtex-6 FPGAs. The high level synthesis flow provides Virtex-6 FPGA users with more automatic target-specific optimizations and architecture exploration from high level models and delivers up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications.

Synopsys announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, has standardised on Synopsys’ IC Compiler physical design solution, a key component of the Galaxy Implementation Platform, to deliver best performance, power and area on MediaTek’s leading-edge wireless communications chips. IC Compiler’s advanced placement, timing and power optimisation along with its...

Synopsys, Inc. today announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, has standardized on Synopsys' IC Compiler physical design solution, a key component of the Galaxy™ Implementation Platform, to deliver best performance, power and area on MediaTek's leading-edge wireless communications chips. IC Compiler's advanced placement, timing and power optimization along...

Synopsys announced the availability of IC Compiler 2010.03, a physical implementation solution delivering up to 2.5X faster performance on multicorner/multimode (MCMM) designs, and enhanced In-Design technology for faster design closure. IC Compiler’s In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has pro...

Synopsys announced the immediate availability of the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications.

Synopsys announced the immediate availability of the DesignWare MIPI 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards.

Synopsys announced the immediate availability of the DesignWare MIPI 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards. The configurable MIPI 4G DigRF Master Controller is compliant to the recently ratified MIPI DigRF v4 1.00 specification and enables desig...

Synopsys announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys' previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs.

Synopsys announced enhanced FPGA synthesis support is available for Actel Corporation's (Nasdaq: ACTL) new SmartFusion™ intelligent mixed signal FPGAs. Synopsys' Synplify Pro® FPGA synthesis tools have been enhanced to offer advanced support and timing optimization for the flash-based FPGA architecture that provides the programmable digital portion of the SmartFusion devices.