Synopsys has announced that its DesignWare DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY also supports the anticipated Low Voltage DDR3L specification that runs at 1.35V, making the DesignWare IP ideal for power conscious designs where the change from 1.5V DDR3 to 1.35V DDR3L can reduce DRAM power consumption by up to ...

Synopsys has announced that Ubixum has used Synopsys’ Galaxy Custom Designer implementation solution to successfully design its latest advanced image sensor chip. The chip has been verified to be product-ready with first silicon. Custom Designer is a modern-era custom implementation solution that delivers superior ease-of-use and leverages Synopsys’ Galaxy Implementation Platform to provide a unified solution for custom and digital designs. T...

Synopsys today announced that Renesas Technology has adopted Synopsys' Proteus OPC for 45nm production. With the introduction of 45nm and below technologies, the demand for optical proximity correction (OPC) becomes greater due to design complexity and layer volume, making time to market and cost of ownership critical factors in OPC vendor selection. Proteus OPC is the industry’s most cost-effective solution since its highly scalable engine ru...

Synopsys has announced that the School of Electronics and Computer Science (ECS) at the University of Southampton is the first Western European university to receive the Charles Babbage Grant from Synopsys. Through the grant, ECS receives licenses of Synopsys' comprehensive electronic design automation (EDA) software and intellectual property. The grant also enabled the University to set up a brand new laboratory for virtual learning.

Synopsys has announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys’ DesignWare IP portfolio. Synopsys’ DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability a...

Synopsys has introduced the latest release of its Galaxy Implementation Platform delivering 2x faster design implementation and signoff throughput with new multicore performance and multi-corner/multi-mode (MCMM) technologies. Built-in support for multicore processing across the Galaxy Platform enables engineering teams to immediately boost runtime performance using their existing compute servers. Additionally, the Galaxy Platform includes new MC...

In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd. , IBM, Samsung Electronics, Co., Ltd., and Synopsys, Inc. (Nasdaq: SNPS) today announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices. The objective of this collaboration i...

Fuzhou Rockchip Electronics Company, Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. today announced that Rockchip has achieved first-time silicon success on its next generation multimedia system-on-a-chip (SoC), using a combination of Synopsys’ tools, intellectual property (IP) and services with Chartered’s 65nm manufacturing technology. The RK28 multimedia SoC, Rockchip’s first mass-production 65nm chip designed in C...

Synopsys has introduced Galaxy Constraint Analyzer, a new tool which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer is an intuitive tool that enables designers to quickly assess the correctness and consistency of timing constraints. Correctness and consistency lead to more efficient runtimes in Synopsys’ Design Compiler synthe...

iPDKsSynopsys has announced that Synopsys and TSMC have entered into a comprehensive multi-year agreement to jointly develop, validate, support and distribute interoperable process design kits (iPDKs) that are optimised for TSMC advanced semiconductor processes including the 65nm, 40nm and 28nm nodes. The agreement is the culmination of a two year collaboration to establish an interoperable PDK ecosystem that can accelerate and broaden designer a...

Synopsys has introduced its In-Design Rail Analysis capability to accelerate design closure. Part of Synopsys’ IC Compiler in-design ecosystem, In-Design Rail Analysis utilises embedded PrimeRail analysis and fixing guidance technology to enable designers to easily perform power network verification throughout physical implementation. By identifying and fixing voltage-drop and electromigration issues earlier in the flow, designers can eliminate...

Synopsys has announced that Achronix Semiconductor Corporation, maker of ultra-fast field-programmable gate arrays (FPGAs), has deployed Synopsys’ IC Compiler and the recently announced IC Validator, the newest addition to the Galaxy(TM) Implementation Platform, for designing their next generation of high end FPGAs.

Synopsys has announced its complete DesignWare IP solution for PCI Express 3.0 consisting of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG(r)) at a preliminary revision 0.5. Synopsys' high-quality DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-c...

Synopsys has announced that NetLogic Microsystems, a leader in the design and development of knowledge-based processors and high speed integrated circuits, has signed an expanded business agreement to establish Synopsys as its primary EDA partner. NetLogic Microsystems chose Synopsys because of its technology leadership and its ability to help NetLogic Microsystems meet its aggressive product schedules.

Synopsys has announced that ST-Ericsson has adopted Synopsys’ MVSIM low power dynamic verification solution for its STw8500 system-on-chip (SoC) platform for the mobile phone market. ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool’s extensive support for the IEEE 1801 [Unified Powe...

Synopsys has announced that Aquantia, the leading innovator in 10GBASE-T networking, has deployed Synopsys’ recently announced IC Validator, the newest addition to the Galaxy Implementation Platform, into production use at 40nm. IC Validator is an ideal add on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within...

Synopsys has announced that Achronix Semiconductor Corporation, maker of ultra-fast field-programmable gate arrays (FPGAs), has signed an expanded business agreement to establish Synopsys as its leading EDA partner for the design of its next generation FPGAs. As a result of the new multi-year agreement, Achronix has consolidated on Synopsys’ Galaxy Implementation and Discovery Verification Platforms throughout its internal development and desig...

Synopsys and Actel Corporation today announced a multi-year extension of their OEM agreement for FPGA design tools. Under the terms of the agreement, Actel maintains rights to provide Actel-specific versions of Synopsys’ Synplify Pro, Identify and Synplify DSP software as part of the Libero Integrated Design Environment (IDE). Actel has been offering these products to its customers for more than 10 years through an OEM agreement with Synplicit...

Synopsys has announced availability of advanced analogue simulation and layout capabilities in its Galaxy Custom Designer(tm) implementation solution. The new features in the 2009.06 release deliver productivity advances to aid analogue circuit designers and layout engineers, enabling Synopsys to further extend its reach in the custom implementation segment.

Synopsys has announced that TSMC selected Synopsys’ Galaxy Implementation Platform for its new Integrated Sign-Off Flow. The RTL-to-GDSII design flow deploys the advanced optimisation technologies of Synopsys’ Design Compiler synthesis and IC Compiler physical implementation solutions, and the PrimeTime sign-off and Star-RCXT extraction solutions—the industry yardsticks for IC design sign-off. The new flow is now available for 65nm designs ...