Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that John Chilton, senior vice president of marketing and corporate development, will speak at the Morgan Stanley Technology, Media & Telecom Conference in San Francisco, on Mar. 1, 2011.

Synopsys announced the immediate availability of the silicon-proven DesignWare Data Converter IP for SMIC's popular 65-nanometer (nm) Low Leakage (LL) process technology, enabling designers to improve their chips' power efficiency and ease their integration efforts. Synopsys is the first IP provider to offer a comprehensive portfolio of high-performance data converter IP solutions consisting of analog-to-digital converters (ADCs) and digital-to-a...

Synopsys and Varian Semiconductor Equipment Associates, Inc. (Nasdaq: VSEA), the leading producer of ion implantation equipment used in the manufacture of semiconductors, today announced a collaboration to develop Technology CAD (TCAD) models for cryogenic ion implantation. By enabling faster optimization of the cryogenic implant process through simulation, the models derived from this collaboration will speed up process development of advanced C...

Synopsys announced the release of its enhanced DesignWare Universal DDR Memory Controller, which delivers up to 30 percent lower latency and offers up to 15 percent higher throughput than the previous generation controller. The DDR Memory Controller offers new features such as high-priority bypass and configurable 'look-ahead.' The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm, allowing imme...

Synopsys announced the broad availability of Platform Architect with Multicore Optimization Technology, a new solution for performance analysis and early definition of multicore system architectures in SystemC. Using Platform Architect with Multicore Optimization Technology, designers of SoCs, chipsets and systems can capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance m...

Synopsys today announced the verification FastForward migration program. The program helps Cadence Incisive and Mentor Graphics Questa users to migrate to the VCS functional verification solution and benefit from its superior technologies. These include: innovative performance engines; the industry's broadest SystemVerilog support for VMM, OVM, and the UVM methodologies; a powerful constraints solver; new coverage closure technologies; unique l...

Synopsys announced new extensions to its open source-licensed Interconnect Technology Format (ITF) which enables modeling of more complex device structures and interconnect layers for parasitic extraction tools at 28-nanometer (nm) and below process technologies. Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) to define th...

Synopsys announced the availability of the latest release of IC Compiler, a key component of the Galaxy Implementation Platform. This development caps a year of leading innovations in physical design productivity. For two years in a row, IC Compiler has won an EDN Innovation Award. In 2010 it won for In-Design Physical Verification. The IC Compiler 2010.12 release advances this capability, making automatic DRC repair up to 7X faster. This latest ...

Synopsys announced the 2010.12 release of its Galaxy Implementation Platform, delivering new technologies to address the scalability, convergence and throughput needs of Gigascale design. Faster runtime performance with multicore processing and innovations to increase design capacity throughout the Galaxy Platform enable engineering teams to gain productivity benefits for large-scale, complex integrated circuit (IC) design. Additionally, the Gala...

Synopsys announced the immediate availability of the DesignWare DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. The DesignWare DDR PHY compiler offers designers a web-based GUI to assemble a customized, high-performance DDR PHY for their system-on-chips (SoCs). The DesignWare DDR PHY compiler evaluates more than 60 variables and allows the evaluation of unlimited 'what-if' scenarios. The output of the PHY compiler is a customize...

Synopsys announced it is delivering a low power, high-performance system-on-chip (SoC) design solution optimized for the Common Platform alliance (CPA) 28-nanometer(nm) high-k metal gate (HKMG) technology. Based on Synopsys' Lynx Design System and its Galaxy™ Implementation Platform-enabled flow with Synopsys DesignWare Interface IP, this solution was built through a multi-year collaboration with ARM and the Common Platform alliance [IBM, Samsu...

Synopsys announced Android operating system (v2.2 FroYo) support for the DesignWare™ ARC™ 750D processor core. The DesignWare ARC 750D host processor, which runs at 1.1 GHz and delivers 1800 DMIPs in an industry standard 40-nanometer (nm) process, is an ideal choice for designers requiring a high-performance, low-power and cost-effective microprocessor to drive Android-based applications. The DesignWare ARC 750D processor now allows designers...

Synopsys, Inc. announced that Mazda Motor Corporation, a leading producer of automobiles, has adopted Synopsys' CoMET-METeor virtual prototyping solution to verify their Electronic Control Units (ECUs). Over the last year, Mazda has been using the METeor embedded software development environment to conduct its ECU system verification in a virtual environment. By decreasing the number of tests on real automobiles and hardware-in-the-loop simula...

Synopsys announced that Nuvoton Technology Corp (TSE:4919), affiliate of Winbond Electronics Corp, standardized on Formality equivalence checking to accelerate verification of its Super I/O chips, displacing their existing solution. Using Formality, Nuvoton designers were able to complete equivalence checking out of the box twice as fast, allowing them to meet their challenging design and schedule goals. This success is now driving broad deployme...

Synopsys announced the availability of two new DesignWare Sonic Focus IP products that enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to significantly enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP are audio post-processing solutions that help restore clari...

Synopsys announced the immediate availability of DesignWare IP for the Mobile Industry Processor Interface (MIPI®) Display Serial Interface (DSI) Host Controller . With this latest addition, Synopsys broadens its DesignWare MIPI IP portfolio consisting of the DigRFSM v3 (2.5G/3.0G) and DigRFSM v4 (4G), CSI-2, M-PHY and D-PHY protocols. The DesignWare MIPI DSI Host Controller is fully compliant to the latest MIPI Alliance specifications for DSI, ...

Synopsys announced it has received the Corporate Award from the IEEE Standards Association (IEEE-SA) for its contribution to semiconductor and Electronic Design Automation (EDA) standards and its role in fostering innovation and collaboration in the standards community. The award is presented annually to an IEEE-SA member who demonstrates outstanding leadership and contributions to the organization.

Synopsys today reported results for its fourth quarter and fiscal year 2010. For the fourth quarter of fiscal 2010, Synopsys reported revenue of $375.5 million, compared to $338.3 million for the fourth quarter of fiscal 2009. Revenue for fiscal year 2010 was $1.38 billion, an increase of 1.5 percent from $1.36 billion in fiscal 2009.

Synopsys today announced the immediate availability of the DesignWare ARC AS 221 BD dual-core processor optimised for high-definition (HD) audio applications. In addition, Synopsys announced three new enhancements to its DesignWare ARC 600 32-bit configurable processor family, including an optional Memory Protection Unit (MPU), Power Management Unit (PMU) and single cycle 16x16 multiplier. The latest features allow designers to incorporate advanc...

Synopsys announced the availability of enhancements to its LightTools® illumination design and analysis software. LightTools version 7.1 delivers new analytical capabilities that speed the development of luminaires, particularly for general lighting and automotive applications. In addition, new user interface features maximize working area and flexibility to help boost designers' productivity throughout the design and verification process.