Synopsys announce that TSMC awarded Synopsys its Open Innovation Platform "Partner of the Year 2013" for joint development of 16-nanometer FinFET design infrastructure. The award recognizes Synopsys' broad and deep technical expertise and shared commitment to the development and delivery of TSMC's 16-nm Reference Flow, validated on a quad-core ARM Cortex-A15 mobile processor design

Synopsys has collaborated with TSMC to provide support for voltage-dependent design rules in TSMC's 16-nm Custom Design Reference Flow. As part of TSMC's custom design infrastructure, TSMC has also certified Synopsys' Laker custom design solution and circuit simulation tools that deliver new capabilities for TSMC V0.5 16-nm FinFET process layout design rules, device models, and electromigration and IR-drop analysis. TSMC and Synopsys will continu...

Synopsys Inc today announced availability of the latest release of its Virtualizer tool set for creating Virtualizer Development Kits (VDKs), software development kits which use virtual prototypes to accelerate embedded software development, debugging and optimization. The new Virtualizer release speeds VDK development by enabling more efficient collaboration among modeling teams, along with easier management and exchange of virtual prototypes fo...

Synopsys announce the availability of a range of DesignWare Interface IP on TSMC's 20-nanometer system-on-chip process. The silicon-proven Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC's 20SoC process reduces risk for designers who need to implement the latest interface IP standards in their SoCs and want to take advantage of 25 percent lower power consumption or a 30 percent performance improvement offered by TSMC's 20SoC pro...

Synopsys announced the industry's first SuperSpeed USB Inter-chip interoperability demonstration. The demonstration shows the successful interoperability between Synopsys' DesignWare USB 3.0 IP for SSIC and Intel Corporation's SSIC development platform, and is on display at the Intel Developer Forum 2013. Developed to reduce power consumption for mobile application processors and wireless chipsets, the SSIC specification from the USB 3.0 Promoter...

Synopsys Inc today announced its DFTMAX Ultra product, part of Synopsys' synthesis-based test solution, that significantly reduces silicon test cost. Embedded in Design Compiler RTL synthesis and incorporating recently unveiled test technology, DFTMAX Ultra delivers up to 3x higher compression, enables testing of several die in parallel and utilizes the maximum performance of tester equipment to minimize silicon test time.

Synopsys have announced availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including analog/mixed-signal IP, digital logic blocks, memory and interface IP.

Synopsys, Inc today announced TSMC's certification of Synopsys' Laker custom design solution for the TSMC 16-nanometer (nm) FinFET process Design Rule Manual (DRM) V0.5 as well as the availability of a 16-nm interoperable process design kit (iPDK) from TSMC. With its robust support for the iPDK standard, Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180-nm to 16-nm. Along with...

Synopsys today launched its DesignWare HDMI 2.0 TX/RX IP solutions, including controller, PHY, and example Linux drivers to reduce designers' integration risk and time-to-market. With aggregate bandwidth of up to 18 Gbps, the DesignWare HDMI 2.0 IP enables 4K x 2K (4400 vertical pixels x 2250 horizontal pixels) resolution at a 60 Hz frame rate in deep color mode to provide a flickerless, ultra high-definition (UHD) viewing experience.

Synopsys Inc today announced that Samsung Electronics has widely deployed the Design Compiler Graphical product, Synopsys' premium RTL Synthesis solution, to reduce power and area to deliver more competitive SoCs for the mobile market. Advanced technologies in Design Compiler Graphical, a key component of Synopsys' Galaxy Implementation Platform, including congestion optimization, advanced placement-based timing optimization and physical guidance...

Synopsys today announced that four students, Matthew Bergkoetter, James Corsetti, and Jonathan Papa, all of the University of Rochester; and Tzu-Yu Wu of the University of Arizona, are the winners of the 2013 Robert S. Hilbert Memorial Optical Design Competition. The competition was established in 2000 by Optical Research Associates (ORA®), now the Optical Solutions Group at Synopsys, and was named in honor of ORA's former president and ...

Synopsys has today introduced the new Dolby MS11 Multistream Decoder optimized for its DesignWare ARC AS211SFX and AS221BD audio processors. Supporting Dolby Digital Plus, Dolby Digital, Dolby Pulse (AAC LC, HE AAC, and HE AAC v.2), the MS11 Multistream Decoder provides television and set-top box manufacturers with a single-package technology solution for decoding all premium audio formats.

Synopsys and Lattice Semiconductor reveal a multi-year extension of their OEM agreement for Synopsys' Synplify FPGA synthesis tools optimized for Lattice FPGAs and Complex Programmable Logic Devices. Under this continued agreement, Synopsys remains the exclusive independent provider of FPGA logic synthesis technology for designers targeting Lattice FPGA and CPLD products.

Synopsys have introduced a complete and integrated hardware and software solution for sensor control applications, the DesignWare Sensor IP Subsystem. Optimized to process digital and analog sensor data, this new IP subsystem offloads the host processor and enables more efficient processing of the sensor data with ultra-low power. Incorporating a DesignWare ARC EM4 32-bit processor, digital interfaces, ADCs, hardware accelerators, software I/O dr...

Synopsys reveal availability of its 28-nanometer DesignWare data converter IP portfolio,which includes analog-to-digital converters, digital-to-analog converters and integrated PLLs. Implementing Synopsys' new data converter architecture in the 28-nm process node resulted in up to 76 percent reduction in power consumption and up to 86 percent reduction in area use, which reduces system costs for wireless networking and mobile communications syste...

Synopsys have announced that Fujitsu Laboratories have used Processor Designer to design a custom digital signal processor for their 3G/LTE multi-mode modem. Traditionally, multi-mode modems have been optimized for power by requiring a hardware block for each mode. By using Processor Designer to develop their own custom-designed DSP, Fujitsu Laboratories was able to develop a processor that handles both 3G and LTE modes and consumes 20 percent le...

Synopsys and United Microelectronics Corporation today announced that the collaboration between the two companies has resulted in the successful tapeout of UMC's first process qualification vehicle in its 14-nanometer (nm) FinFET process utilizing Synopsys' DesignWare Logic Library IP portfolio and StarRC parasitic extraction solution, a part of the Galaxy Implementation Platform.

Synopsys today announced the industry's first M-PCIe interoperability demonstration. The demonstration will be shown at the PCI-SIG Developers Conference 2013 and shows the successful interoperability between M-PCIe interfaces from Synopsys and Intel using M-PCIe-based switch and endpoint devices.

Synopsys announced that it will join Singapore's A*STAR Institute of Microelectronics -led 2.5D TSI Consortium to provide the framework for heterogeneous 3D-IC systems using through-silicon interposer technology. Synopsys will contribute its market expertise to the consortium to optimize TSI technology for cost-effective and performance-driven applications. The consortium's research and development efforts will lead to the demonstration of a hete...

Synopsys today announced that OCZ Technology Group has achieved first-pass silicon success for its NAND flash Vector SSD using Synopsys' DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System solution and Professional Services.