Synopsys has announced availability of the V1.0 certified solution for cell-based and custom implementation with the TSMC N16 FinFET process. The TSMC-certified solution delivers predictable design closure with production-ready FinFET design automation tools, allowing engineers designing next generation semiconductors to deliver faster, more power-efficient and denser chips.

Expanding the company's portfolio of Virtualizer Development Kits (VDKs), Synopsys has announced the RH850/E1x series reference virtual prototype. Targeting powertrain Electronic Control Units (ECUs), this VDK enables automotive engineers to start software development, integration and test, months before hardware is available. This helps to reduce development cost and speed time to market.

The publication of Better Software. Faster!, a practical guide for using virtual prototypes, has been announced by Synopsys. Virtual prototypes are fast, fully functional software models of systems that execute unmodified production code and provide development, debug and analysis efficiency, which mitigate software development challenges, increase productivity, resulting in better products faster. 

Synopsys have announced that they have completed  its acquisition of Coverity, a provider of software quality, testing and security tools. The value of the transaction is approximately $334m net of cash acquired, which Synopsys is funding using a combination of cash and approximately $200m in debt. 

An initiative to accelerate the verification of mixed-signal SoC designs has been announced by Synopsys. The company has launched the initial components of the initiative, which include a SystemVerilog-based methodology, AMS Testbench, and the VCS AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim FastSPICE simulator. 

Synopsys have presented what they call a 'game-changing' successor to their IC Compiler, offering ultra-high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques. The IC Compiler II has been built from the ground up on a completely new, multi-threaded infrastructure.

MediaTek has initiated deployment of Synopsys' IC Compiler place and route solution for hierarchical design implementation. This collaboration extends the deployment of IC Compiler to the full flow starting from hierarchical design planning, through top and block-level place and route to final chip assembly.

The DesignWare ARC Software Development Platforms from Synopsys accelerates software development and debug of ARC processor-based SoC designs. The ARC AXS101 and AXS102 Software Development Platforms are complete and ready-to-use hardware and software platforms that include ARC processors, peripherals, pre-built Linux and MQX operating systems, device drivers, and application examples, enabling designers to start software development prior to SoC...

Synopsys has announced that STMicroelectronics has standardized on Synopsys' IC Compiler place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization.  STMicroelectronics processor cores are known for pushing gigahertz performance with extreme energy efficiency, making them a compelling choice for the mobile market place.

A product which represents a compelling vision of SoC verification technology and verification roadmaps has been unveiled by Synopsys. Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure. 

Synopsys and Imagination Technologies have entered into a collaboration to enable designers to speed verification and hardware/software bring-up of SoCs containing Imagination Technologies' PowerVR Series6 GPU cores using ZeBu Server emulators.

Providing software tools to design and program application-specific instruction-set processors (ASIPs), Target Compiler Technologies has been acquired by Synopsys. This acquisition strengthens Synopsys' existing ASIP tools portfolio and brings a world-class team of ASIP experts into the company.

Designed to accelerate complex IP and subsystem prototyping, the HAPS Developer eXpress (HAPS-DX) from Synopsys is an extension of their HAPS FPGA-based prototyping product line. The prototyping system includes customized synthesis and debug software to speed prototype bring-up and streamline the transition from individual IP blocks to full system-on-chip (SoC) validation. The system provides a seamless prototyping solution from IP to full SoC fo...

Version 8.1 of the illumination design software, LightTools, has been announced by Synopsys. Featuring speed improvements for tracing backward rays and generating photorealistic images, this enhanced version provides new modeling and analysis features for general lighting, automotive and biomedical applications.

The industry's first SuperSpeed USB 10 Gbps (USB 3.1) platform-to-platform Host-Device IP data transfer has been achieved by Synopsys. The IP realized 10 Gbps USB 3.1 effective data rates of more than 900 MBps between two Synopsys HAPS-70 FPGA-based prototyping systems while using backward-compatible USB connectors, cables and software.

Abilis Systems has achieved first-pass silicon success with its TB100 8-channel broadcast-to-IP secure media processor for the digital TV consumer market. Abilis achieved this success using a broad set of Synopsys design solutions including DesignWare ARC Processors, Interface IP, Embedded Memories with integrated test and repair, Lynx Design System and Professional Services.

The new DesignWare AEON Multiple-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP has today been made available by Synopsys. Optimized for the stringent power and area requirements of wireless and RFID/NFC ICs, the DesignWare AEON MTP ULP NVM IP cuts power consumption by up to 90% compared to the previous generation by offering a single-bit read capability, read operation down to 0.9V and peak current under 10uA during e...

Synopsys and CEVA have collaborated to create highly optimized implementations of the CEVA-XC DSP cores targeting the high-performance needs of base-station applications and the low-power requirements of handset applications. CEVA used Synopsys' DesignWare High Performance Core (HPC) Design Kit to optimize its DSP for performance, power and area, achieving an 8 percent improvement in performance at 1.3 GHz maximum operating frequency for its base...

The new extended Platform Architect has been announced by Synopsys. The extended Platform Architect includes multicore optimization (MCO) technology performance exploration solution for ARM AMBA 4 interconnect-based SoCs to support ARM CoreLink NIC-400 network interconnect-based designs. Synopsys Platform Architect MCO and Synopsys' new SBL-400 SystemC model of the ARM CoreLink NIC-400 network interconnect enable SoC architects to efficiently ex...

Synopsys, Inc. today announced availability of the new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications. The 32-bit ARC EM SEP processor is based on the highly efficient ARC EM4 core. It delivers performance up to 300 MHz and power consumption as low as 16 mW/MHz on typical 65-nanometer (nm) low power silicon processes, with integrated hardware safety features that enable ASIL D compli...