Synopsys announced Formality Ultra, a new configuration of the Formality equivalency checking solution. Formality Ultra includes innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes for multimillion instance designs. These new capabilities will help designers cut in half the time they spend ...

Synopsys is pleased to announced today an extension to its DesignWare Duet Embedded Memory and Logic Library IP portfolio specifically designed to enable the optimized implementation of a broad range of processor cores.

Synopsys today unveiled a new, innovative test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die.

Synopsys announced the availability of a comprehensive design implementation solution for the Samsung 14LPE FinFET process. The solution includes new fast-field-solver technologies to model the effect of 3-D structures for parasitic extraction, accurate high-performance models for device simulation, and comprehensive support for new rules for physical design implementation.

Synopsys announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16-nm FinFET process Design Rule Manual and SPICE V0.1. TSMC's certification is built on early collaboration for extraction and modeling of 3-D parasitics in FinFET devices and extends to full-line design implementation solutions.

Synopsys today announced availability of the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The DesignWare ARC EM4 and ARC EM6 processor cores are optimized for use in embedded and deeply embedded applications such as sensors, storage devices, appliances, consumer electronics, and battery-operated devices where high performance, small size and minimal power consumption are essential.

In the world of application-specific processor design, architects require highly automated software development tools to efficiently architect their design. To aid architects in their design challenges, Synopsys and ACE Associated Compiler Experts have extended their multi-year collaboration to integrate ACE's optimized compiler technology with Synopsys' Processor Designer product line.

Synopsys, Inc today announced the availability of the Virtualizer Development Kit (VDK) for Renesas RH850 MCUs to accelerate software development, system integration and test for RH850-based automotive applications such as body, powertrain/hybrid and chassis/safety control. VDKs are software development kits integrating design-specific virtual prototypes with software debug and analysis tools.

Synopsys today announced that its DesignWare PHY and digital controller IP for the PCI-SIG PCI Express 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCI Express 3.0.

Synopsys today announced that Achronix Semiconductor has successfully used both Synopsys' IC Compiler physical design and IC Validator physical verification solutions to sign off its Speedster22i FPGA – the industry's first system-on-chip design using FinFET transistors.

Synopsys announced it will report results for the second quarter fiscal year 2013 on Wednesday, May 22, 2013, after the market close. A conference call to review the results will begin at 2:00 p.m. PT (5:00 p.m. ET) and will be hosted by Aart de Geus, chairman and co-chief executive officer, and Brian Beattie, chief financial officer.

Synopsys announce that HiSilicon Technologies has taped out a 50+ million instance ARM Cortex-A15 processor based SoC using Synopsys' IC Compiler, a key component of Synopsys' Galaxy Implementation Platform. The latest technology innovations in IC Compiler, including improved clock tree synthesis and faster top-level closure, were key to meeting performance and schedule on this gigascale SoC.

Synopsys today announced the availability of Synopsys' Virtualizer Development Kit for Freescale Semiconductor's Qorivva microcontroller family to accelerate the development of automotive control applications in powertrain/hybrid, chassis/safety and body electronic control units.

Synopsys today announced the availability of the 2013.03 release of its IC Compiler software, a key component of Synopsys' Galaxy Implementation Platform. Adding to the market-leading foundation of design closure technologies already available in IC Compiler, this latest release features innovations to speed design as well as enables the latest process nodes.

Synopsys today announced the immediate availability of the Embedded Vision Development System, an integrated solution for the acceleration of the design of processors for embedded vision based on Synopsys' Processor Designer tool set and Synopsys' HAPS FPGA-based prototyping system.

Synopsys are pleased to announce today that LG Electronics has adopted the IC Validator, Synopsys' physical verification applications tool, as part of their design implementation flow just for ARM processors. Key to LG Electronics' adoption was IC Validator's In-Design technology integration with Synopsys' IC Compiler™ place-and-route solution.

Synopsys today announced that Fujitsu Semiconductor is successfully shipping a 2G/3G/4G baseband processor using Synopsys' DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP. Fujitsu Semiconductor selected Synopsys' silicon-proven IP to mitigate project schedule risks and help ensure the long-term interoperability of their ASIC design customer's system-on-chip with Fujitsu Semiconductor's RFIC products.

Micronas and Synopsys Inc today announced that Micronas has standardized on Synopsys' custom and digital solutions for the design and verification of semiconductors used in automotive and industrial applications. The solution includes Galaxy Custom Designer for custom IC design, HSPICE for circuit simulation, StarRC for gate-level and transistor-level extraction, IC Compiler for place and route, IC Validator for physical verification and VCS for ...

Synopsys announce immediate availability of its PrimeTime ADV solution, a new configuration of its market-leading PrimeTime static timing analysis and signoff product. PrimeTime ADV includes advanced leakage recovery and will incorporate physical-aware signoff-driven engineering change order guidance technology, which work in conjunction with the latest innovations for Synopsys' IC Compiler solution to enable the fastest path to timing closure an...

Synopsys reveal advances in its Galaxy Implementation Platform with the introduction of Galaxy Custom Router technology. The new Galaxy Custom Router provides automatic routing for complex high-speed digital and mixed-signals nets that require carefully crafted, high-quality layouts, such as shielded buses or nets, differential pairs, twisted pairs and matched resistance and capacitance routing.