Claiming to be up to 75% smaller than alternative NVM IP solutions, the DesignWare AEON Trim NVM IP for high-voltage processes has been launched by Synopsys. Faster programming times reduce NVM test times by 3X compared to alternative NVM solutions, enabling designers to reduce production test times and minimize test costs for automotive and industrial ICs.

In a bid to advance the modeling of negative bias temperature instability (NBTI), Synopsys have announced a collaboration with the Indian Institute of Technology. The collaboration aims to provide semiconductor manufacturers with an insight into NBTI degradation and develop methods to mitigate its effects on FinFETs at the 14nm node and beyond.    

Synopsys, Inc announced the immediate availability of a wide range of DesignWare interface, analog, logic library and embedded memory IP for TSMC's 28-nanometer (nm) high-performance compact (HPC) process. Synopsys' production-ready DesignWare IP reduces risks for designers who want to take advantage of the lower power consumption, area reduction and performance improvements that the TSMC 28HPC process offers. The DesignWare IP portfolio for the ...

Synopsys, Inc announced the IP Accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their system-on-chips (SoCs). This initiative augments Synopsys' established broad portfolio of silicon-proven DesignWare IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With ...

Synopsys, Inc announced certification and immediate availability of a comprehensive design solution and semiconductor intellectual property (IP) for Samsung's 14-nm FinFET process. 

Synopsys, Inc announced the launch of its HAPS Connect Program to broaden hardware and service offerings for Synopsys HAPS  prototyping systems. Back9 Design, eInfochips, Fidus, Gigafirm, hd Lab and Sarokal are the first companies to sign multi-year agreements to provide daughter boards, mechanical design services and protocol testing for Synopsys HAPS systems. 

Synopsys has announced the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.

Synopsys has announced the release of its DDR4/3 and LPDDR4/3/2 Verification IP (VIP) available as part of Synopsys' Verification Compiler solution and as standalone titles.  Based on 100 percent native SystemVerilog, the memory VIP includes built-in support for RDIMM and LRDIMM models, Verdi Protocol Analyzer debug capability and integrated verification plans, all designed to enable users to accelerate the verification of memory interfaces ...

Synopsys has announced it has extended its collaboration with STMicroelectronics to include Samsung Electronics, enabling broader market adoption of ST's 28-nm FD-SOI technology for SoC design. Synopsys' Galaxy Design Platform is production-proven on multiple designs based on ST's 28-nm FD-SOI technology.

A broad SoC design enablement for Intel's 14nm Tri-Gate process technology, for use by customers of Intel Custom Foundry, has been announced in a joint statement by Synopsys and Intel. The Intel Custom Foundry 14nm design platform supports Synopsys' industry-leading Galaxy Design Platform tools and RTL to GDSII methodology, high performance DesignWare Memory Compiler IP, and advanced interface IP.

Designed for low-power embedded digital signal processing applications, the DesignWare ARC EM DSP family of processors has been introduced by Synopsys. The processors are implementations of the ARCv2DSP instruction set architecture (ISA), an enhancement to the efficiency-optimised ARCv2 ISA with over 100 new DSP instructions for accelerating signal processing algorithms, including vector and complex MUL/MAC operations.

A complete PCI Express 4.0 IP solution, which Synopsys claims as an industry first, is now available to designers. Consisting of DesignWare PHY, controllers and verification IP, the solution targets enterprise computing applications such as servers, networking, storage systems and SSDs. The PCI Express 4.0 specification doubles throughput to 16 GT/s and is currently at a preliminary revision 0.3 within the PCI Special Interest...

The validation of DesignWare IP in the TSMC 16-nm FinFET process technology has been announced by Synopsys. Designers developing SoCs in TSMC's 16-nm FinFET process can take advantage of the doubled transistor density, which reduces power consumption by up to 55% or increases performance by up to 35% compared to TSMC's 28-nm process.

Providing manufacturers with a single technology solution for decoding all DTS 5.1 channel audio formats, Synopsys have made available the DTS-HD audio decoder optimised for its DesignWare ARC AS211SFX and AS221BD Audio Processors.

Synopsys says that Dialog Semiconductor has successfully deployed Synopsys' DFTMAX Ultra product on a mixed-signal test chip to lower manufacturing test costs.  Built into Synopsys' Design Compiler RTL synthesis and linked to Synopsys' TetraMAX ATPG, DFTMAX Ultra was deployed on the design in a single day and delivered 3X higher time compression.

A supplier of end-to-end interconnect solutions for data center servers and storage systems, Mellanox Technologies, has standardized on Synopsys' Design Compiler Graphical RTL Synthesis solution for the design of their interconnect products. The deployment of Design Compiler Graphical has resulted in a Mellanox realising a 10% higher performance, lower area and a highly convergent design flow.

The area of USB PHY implementations has been reduced by up to 50% using DesignWare USB femtoPHY IP from Synopsys. Minimising USB PHY silicon footprint and cost for designs in 28nm and 14/16nm FinFET processes, the DesignWare USB femtoPHYs enable designers to implement the IP in advanced process technologies and reduce SoC design risk. 

Synopsys has announced the availability of Synopsys' ProtoCompiler software for Synopsys' HAPS FPGA-based prototyping systems. ProtoCompiler is an integrated prototyping tool set with built-in HAPS hardware knowledge, which enables the rapid bring-up of a prototype up to 3X faster than existing prototyping flows. ProtoCompiler also enables more efficient prototyping with HAPS by providing an automated partitioning engine, integrated deb...

Synopsys and United Microelectronics Corporation have announced that UMC has certified Synopsys' IC Validator product for physical verification on the company's 28nm process. Joint customers can now reap the benefits of IC Validator for In-Design with confidence that the tool and its runsets have been fully qualified by UMC for accuracy and completeness.

A complete LPDDR4 IP has been launched with the company, Synopsys, claiming it is the industry's first complete LPDDR4 IP solution. The IP includes Synopsys' DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller (uMCTL2) and verification IP (VIP), as well as hardening and signal integrity services.