Synopsys' IC Validator product has been certified by SMIC for signoff physical verification of their 28nm PolySiON (PS) manufacturing process. This provides mutual customers with access to a wider selection of signoff tools for physical verification. Fully qualified Design Rule Checking (DRC) and Layout-Versus-Schematic (LVS) runsets are available for download from the SMIC website.

To achieve a 10% reduction in total die size while maintaining product quality and performance, Marvell Semiconductor have utilised Synopsys' MMB (Multi-Memory Bus) processor for it's networking SoC. The processor, from Synopsys' DesignWare STAR Memory System, allowed Marvell to accelerate silicon bring-up and achieve silicon success.

Synopsys says that VIA Technologies has successfully taped out a system-on-chip (SoC) design using Synopsys' DFTMAX Ultra compression, meeting test time and quality goals. The need to shorten test time in conjunction with increasing design complexity drove VIA Technologies requirement for higher test compression. DFTMAX Ultra and Synopsys' TetraMAX ATPG delivered 11X higher compression while maintaining high test quality and requiring only one we...

The DesignWare STAR Memory System for Embedded Flash product from Synopsys is claimed to be the industry's first integrated memory test and repair solution with test algorithms optimised for on-chip embedded flash memories. It is an automated pre- and post-silicon memory test, diagnostic and repair solution that enables designers to improve test coverage, reduce design time, lower test costs and maximise manufacturing yield.

Synopsys has announced availability of the DesignWare ARC HS38 Processor, the latest addition to the ARC HS Family of high-speed processor IP cores. Like the previously-released HS34 and HS36 processors, the 32-bit ARC HS38 is optimised for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm2) with additional features to support embedded Linux and other high-end operating systems.

Synopsys has developed its Verdi Coverage advanced planning and coverage technology to address the growing challenge of verification closure for complex system-on-chips (SoCs). It introduces advanced technology that allows users to quickly create efficient verification plans, integrate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking,...

Synopsys will host its annual Test Special Interest Group (SIG) event during the International Test Conference (ITC) 2014 in Seattle (Oct 21-23). Delegates will hear a plenary keynote speech from Synopsys Chairman and co-CEO Dr. Aart de Geus, and be able to attend numerous technology sessions featuring Synopsys test experts throughout the three-day conference.

HiSilicon Technologies, an end-to-end chipset solution provider for telecom network, wireless terminal and digital media, has chosen Synopsys' PrimeTime ADV product for timing closure. The innovations in PrimeTime ADV, including signoff-driven, physically-aware engineering change order (ECO) and power recovery, were essential to accelerating design closure on key HiSilicon projects.

A VIP for the M-PCIe protocol, including built-in M-PHY as defined by the MIPI Alliance specification, has been released by Synopsys. Enabling enhanced performance, ease of use and debug in SystemVerilog UVM environments, the VIP is based on the company's native SystemVerilog VIP architecture. The addition of M-PCIe technology to Synopsys' VIP for PCI Express architecture provides designers with a full-featured, SystemVerilog UVM solution to acce...

Synopsys Incannounced that Fujitsu Semiconductor Limited achieved over 30 percent reduction in leakage power consumption while maintaining industry-leading performance for its MB86S70 high performance application processor for imaging. Fujitsu Semiconductor's success in attaining the power-performance goal was enabled by the unique physical guidance flow and leakage-power recovery technologies built into Synopsys' Design Compiler Graphical tool, ...

Saving months on the time-to-market for complex SoC designs, Synopsys has introduced Verification Continuum. The platform accelerates industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs. The verification tool provides virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug, verification IP, planning and coverage technology.

Synopsys have announced that a number of customers using it's Design Compiler RTL synthesis solution have achieved smaller design areas. To reduce system costs or incorporate additional functionality without increasing die size, area optimisation is particularly important for designers across a wide range of electronic applications. 

VIP (Verification IP) for the MIPI Alliance MIPI C-PHY specification is now available from Synopsys. Using three-phase digital coding techniques, the VIP provides higher performance for camera, display and SoC interfaces without affecting bandwidth. As a member of the MIPI Alliance, the company provides VIP and design IP that accelerate the adoption of MIPI-based standards in mobile and mobile-influenced industries.

Using Synopsys' DesignWare MIPI D-PHY and DSI Host Controller IP, the application processor SoC from Leadcore Technology has achieved first-pass silicon success. By using the DesignWare MIPI IP, Leadcore met their area and power requirements for the INNOPOWER LC1810 SoC and delivered production-ready designs four months ahead of schedule. 

The IC Compiler, a place and route product, has been released by Synopsys. As part of the company's Galaxy Design Platform, the product supports FinFET-based design. The tool features look-ahead technology, which predicts downstream processing at early stages of the design when all the information, such as detailed wiring, is not yet available.

Synopsys have increased the performance of it's DesignWare MIPI D-PHY to 2.5Gb/s per lane and decreased it's area and power consumption by 50%. In doing this, the company have extended the battery life for mobile, consumer and automotive applications, and reduced SoC cost.

Enhancing its OptSim modelling capabilities, Synopsys has announced the RSoft OptSim Circuit, an extension of the company's OptSim fibre optic systems modelling tool. Combined, OptSim Circuit and OptSim enables users to automate the design of next-gen single- and multi-stage Photonic Integrated Circuits (PICs).

For on-chip buses, interfaces and memories used on SoC designs, Wipro has used Synopsys' portfolio of SystemVerilog UVM-based verification IP (VIP). Within its UVM testbench environments, Wipro uses this portfolio to reduce verification time, increase quality and accelerate customer schedules.

DesignWare USB 3.0 Controller and PHY IP, manufactured by Synopsys, has shipped more than 100m production SoCs used in mobile computing, digital home and cloud computing applications. The DesignWare USB 3.0 Controller and PHY IP has been integrated into the SoCs of products from more than 60 companies, including Microsoft's XBOX One.

Synopsys has announced that Emulex has adopted it's Verification IP (VIP) for the Ethernet 1G/10G/40G/100G protocol. This is based on Synopsys' SystemVerilog and UVM architecture, offering ease of use, ease of integration, performance, configurability, coverage, and debug within UVM environments. The VIP also supports Synopsys' Protocol Analyzer, a protocol-centric debug environment.