Synopsys has announced the availability of its Virtualizer tool for creating VDKs (Virtualizer Development Kits), software DevKits that use virtual prototypes as the embedded target to enable the fastest time to quality software. The latest Virtualizer release integrates a number of features, including MultiSim, SimSight and FastBuild to increase VDK simulation performance by up to five times and accelerate VDK availability for earlier software d...

Synopsys has announced the availability of verification IP for the MIPI Alliance SoundWire 1.0 specification. Synopsys verification IP for MIPI SoundWire is based on a native SystemVerilog UVM architecture to enable IP, subsystem and SoC designers to easily integrate their designs and accelerate verification performance.

Synopsys and Hardent have announced availability of a compliant and interoperable Display Serial Interface (DSI) solution that helps reduce the data transmission bandwidth in Ultra-High Definition (UHD) mobile devices. By using Hardent's VESA display stream compression Encoder IP, video signals can be compressed and transmitted through Synopsys' DesignWare MIPI DSI Host Controller IP. This enables higher-resolution displays with reduced bandwidth...

Synopsys has announced that it will continue to sell, ship and support its high-performance ZeBu server emulation systems worldwide. They have also released an updated version of ZeBu Server software that does not include the two features previously found to infringe on a Mentor Graphics patent. The release also includes technology for up to three times faster compile performance and Unified Debug with the market-leading Verdi solution.

Synopsys has announced that its Galaxy Design Platform enables 90% of the production tapeouts of FinFET-based designs. The company has also highlighted the use of its Galaxy Design Platform by HiSilicon Technologies, for the implementation of ARM Cortex-A72, Cortex -A57 and Cortex -A53 processor-based FinFET designs targeting TSMC's 16nm process technology.

Synopsy has launched the embARC Open Software Platform to help accelerate the development of DesignWare ARC processor-based embedded systems. The embARC platform gives ARC software developers online access to a comprehensive suite of free and open-source software that eases the development of code for the IoT and other embedded applications.

A place-and-route solution, developed by Synopsys, has enabled Toshiba to accelerate tapeout of an advanced 40nm SoC. The outstanding speed-up and QoR delivered by IC Compiler II enabled Toshiba to achieve higher designer productivity and better device performance. Driven by this tapeout success, Toshiba has commenced the rollout of its IC Compiler II-based design kit throughout their design teams.

Synopsys has announced the availability of its VDK for Freescale's S32V200 family of MCUs. The VDK uses the S32V234 virtual prototype as an embedded target for early and more efficient software development, integration and test of ADAS. 

Synopsys and Hillcrest Labs have announced that Hillcrest's Freespace MotionEngine software is now optimised to run on Synopsys' DesignWare Sensor and Control IP Subsystem. Hillcrest's MotionEngine software transforms sensor data into high quality, contextual information that powers sensor-enabled features on a wide range of devices.

Synopsys and Sensory have announced the availability of an optimised port of Sensory's TrulyHandsfree voice control software for the Synopsys DesignWare ARC EM DSP processor family. In typical 28nm process technologies, the ARC EM5D processor consumes less than 1μW of power executing TrulyHandsfree low-power sound detection software, and less than 40μW operating in speech recognition mode. The combination of Sensory's highly optimised voice...

Synopsys has announced the DesignWare DDR Explorer performance analysis tool, which enables designers to quickly optimise Synopsys' DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) for performance, power and cost. Using DDR Explorer, designers can analyse their DDR memory subsystem and optimise their architecture to increase efficiency by up to 20%, while achieving 10 times faster turnaround time compared to RTL analysis.

The Virtualizer Dev Kit (VDK), developed by Synopsys, now supports Ethernet AVB and CAN-FD automotive network peripherals. Designed for Renesas' RH850 MCU family, the VDK is a software development kit that uses RH850 virtual prototypes as a target with software debug and analysis tools. 

Synopsys has announced that its collaboration with ARM to bring the power of 10X throughput of IC Compiler II place-and-route solution is enabling superior implementation of high-frequency, power-efficient designs by delivering a reference implementation flow for the ARM Cortex-A72 processor. The combination of RTL synthesis and place-and-route solutions with a reference implementation flow optimised for the CPU is already enabling engineers to d...

A verification IP (VIP) for the 25G/50G Ethernet specification, developed by the 25 Gigabit Ethernet Consortium, is now available from Synopsys. Based on native SystemVerilog Universal Verification Methodology (UVM) architecture, the VIP enables easy use, easy integration and improved performance.

A medium density NVM IP family, which fills the gap between lower bit count NVM and flash memory, without requiring additional masks or processing steps, has been released by Synopsys. The DesignWare medium density NVM IP family provides up to 64 Kb of on-chip memory and eliminates the need for external EEPROM or flash memory when integrating MCUs in analogue IC designs for smart sensors, power management and touchscreen controller applications. ...

Moving to a virtual development environment for automotive control embedded software. By Marc Serughetti, Synopsys.

The DesignWare HDMI 2.0 TX and RX controller and PHY IP, developed by Synopsys, have been certified by an HDMI authorised testing centre. The company’s HDMI 2.0 IP with Elliptic Technologies' HDCP embedded security module also achieved HDCP 2.2 certification, enabling the highest content protection over the HDMI 2.0 interface for HD multimedia SoCs.

Synopsys has expanded its memory Verification IP portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and SoC designs.

Synopsys has announced that Fuzhou Rockchip achieved first-pass silicon success for its mobile application processor SoC using a wide range of Synopsys' DesignWare IP. Rockchip reduced time-to-market by months and made a head start over their competition in the fast-moving mobile industry by integrating DesignWare PHY and Controller IP for a range of USB, HDMI and MIPI IP.

Enabling over 50 successful tapeouts in the nine months since it became generally available, Synopsys' PrimeTime ADV advanced timing closure and signoff solution has been adopted by more than 70 leading semiconductor companies. According to Synopsys, the key to its adoption is ease of integration into existing timing closure flows, fast turnaround time and the ability to reduce timing Engineering Change Order (ECO) iterations on designs.