Synopsys has announced FastSPICE simulation breakthroughs in its CustomSim circuit simulator 2015.06 release that doubles multi-core speed-up on four cores, enabling design teams to keep pace with the increasing complexity of verifying advanced-node and mixed-signal designs. Optimisations in CustomSim deliver double single-core speed-up for designs using BCD (Bipolar-CMOS-DMOS) process technology, such as PMICs.

Synopsys and TSMC are collaborating to develop an integrated IoT platform on TSMC's 40nm ultra low power process technology. The platform incorporates a broad range of DesignWare IP, including an integrated sensor and control IP subsystem with the ultra low power ARC EM5D processor core, power- and area-optimised logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an ADC.

Signing a definitive agreement, Synopsys is to acquire Atrenta. By integrating Atrenta's complementary static verification and implementation technology with Synopsys' Verification Continuum and Galaxy Design platforms, Synopsys can offer designers a more comprehensive, robust portfolio of silicon to software solutions for today's complex electronic systems.

Synopsys has announced Intel Custom Foundry's certification of digital and custom implementation tools from the Synopsys Galaxy Design Platform for Intel's 14nm tri-gate process technology. The certification enables customers of Intel Custom Foundry to realise predictability in design closure while taking advantage of the power and performance benefits of the 14nm tri-gate process. In addition, Intel Custom Foundry offers a SoC design flow for 14...

Synopsys has announced that Toshiba and Nationz, a Chinese chip provider, have both successfully deployed Synopsys' PrimeRail tool as the standard power and rail analysis solution for implementation and signoff. The adoption of PrimeRail dynamic analysis in Nationz' design and signoff methodology enabled engineers to accurately capture peak power and voltage drop violations accounting for transient circuit behaviour. 

Synopsys has announced that STMicroelectronics has taped out its latest Fully Depleted Silicon On Insulator (FD-SOI) SoC using Synopsys' IC Compiler II place and route solution. Collaborating closely with Synopsys, ST used the tool to complete more than half of the chip, achieving higher designer productivity and better device performance.

Synopsys has announced it has signed a definitive agreement to acquire certain assets of Quotium, including the Quotium Seeker product and R&D team. The additional talent, technology and products will expand Synopsys' presence in the application security market by extending the Coverity platform with Interactive Application Security Testing (IAST) functionality.

Synopsys has expanded its Virtualizer Development Kit (VDK) portfolio for Renesas' RH850 MCU with a virtual prototype for the RH850/P1x series targeting chassis ECUs. The latest virtual prototype builds upon the existing VDK for Renesas RH850 MCUs, which includes support for the F1x, E1x and C1x series MCUs. 

Synopsys has announced the industry's lowest power controller and PHY IP solution for PCI Express 3.1 specification, reducing active and standby power consumption for mobile SoCs. DesignWare IP for PCIe 3.1 incorporates L1 sub-states along with power gating techniques including the use of power switches, power islands or retention cells to reduce standby power to less than 10μW/lane.

Synopsys has announced that Broadcom has extended its license agreement, providing access to Synopsys' DesignWare ARC processors for an expanded range of advanced multimedia and networking SoC designs. Broadcom has standardised on Synopsys ARC processors to deliver advanced video compression capabilities in its SoCs for high-volume consumer devices.

Synopsys has announced the availability of Verification IP (VIP) for the DDR4 3D Stacking (3DS) specification. Synopsys VIP for DDR4 3DS, based on its native SystemVerilog UVM architecture, is architected for ease of integration and configurability. The VIP for DDR4 3DS supports all JEDEC commands and provides pre-built DIMM (UDIMM, RDIMM, LRDIMM) models with protocol and timing checks, including support for memory vendor and the JEDEC standard p...

Synopsys has expanded its IP Accelerated initiative with support for ARM processors with the DesignWare Hybrid IP prototyping kits. The kits enable designers to prototype the ARM processor and memory elements of a design in a virtual environment for superior debug visibility, and to develop software for the DesignWare interface IP in an FPGA-based environment for high-performance execution with real-world interface connectivity. 

Synopsys has released extensions to its open-source Interconnect Technology Format (ITF) which enable modelling of complex device and interconnect parasitic effects at the advanced 10nm process node. The extensions include modelling of variation effects due to Multi-Patterning Technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB), an IEEE-ISTO Federation Member Program, to define an...

Synopsys has announced it has signed a definitive agreement to acquire Codenomicon. The additional talent, technology and products will expand Synopsys' presence in the software security market segment and extend the Coverity quality and security platform to help software developers throughout various organisations quickly find and fix security vulnerabilities and protect applications from security attacks.

To enable designers to integrate required functionality in mobile and enterprise SoCs with less risk, Synopsys has introduced a portfolio of DesignWare PHY IP for TSMC's 16nm FinFET Plus (16FF+) processes. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCIe 4.0, 3.0 and 2.0; SATA ...

Synopsys has announced that TSMC has concluded 16nm FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys' custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys' Galaxy Design Platform for 16nm production designs and 10nm early engagements.

Synopsys has announced the availability of version 2.0 of its LucidShape automotive lighting design software, which delivers a powerful photorealistic visualisation module for efficient performance evaluations early in the design cycle, as well as productivity-enhancing tools to enable faster, more accurate model creation. LucidShape 2.0 empowers automotive lighting engineers to develop, verify and deliver high-quality designs while reducing prod...

Fully programmable and configurable vision processor IP cores, which combine the flexibility of software solutions with the low cost and low power consumption of dedicated hardware, have been introduced by Synopsys. The DesignWare EV52 and EV54 processors implement a Convolutional Neural Network that can operate at more than 1000GOPS/W, enabling fast and accurate detection of a wide range of objects such as faces, pedestrians and hand gestures at...

A tool which speeds the design of ASIPs (Application-Specific Instruction-set Processors) has been released by Synopsys. The ASIP Designer's language-based approach allows the automatic generation of synthesisable RTL and SDKs from a single input specification, accelerating the processor design and verification effort by up to five times compared to traditional manual approaches. ASIPs are deployed in a wide range of signal-processing intens...

Synopsys now has more than 200 debug and analysis apps available on the VC Apps Exchange portal and in the Verdi VC Apps Toolbox, demonstrating rapid momentum for customised applications that drive continuous innovation and further enable SoC teams to address their debug challenges.