Search results for "chiplet"

Alphawave Semi has unveiled a 9.2 Gbps HBM3E sub-system (PHY + Controller IP) silicon platform.

Alphawave Semi, a global pioneer in high-speed connectivity and compute silicon for the world’s technology infrastructure, has announced a 9.2Gbps HBM3E sub-system (PHY + Controller IP) silicon platform.

Renesas Electronics Corporation recently unveiled its strategy for the forthcoming generation of system on chips (SoCs) and microcontrollers (MCUs), aimed at a broad spectrum of automotive digital applications.

Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tapeouts.

Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tapeouts.

Cadence has announced the new Cadence Voltus InsightAI, a generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA).

ITEC has introduced the ADAT3 XF TwinRevolve flip-chip die bonder, which runs five times faster than existing machines, attaching up to 60,000 flip-chip dies per hour.

Socionext announced a collaboration with Arm and TSMC for the development of a power-optimised 32-core CPU chiplet in TSMCʼs 2nm silicon technology, delivering scalable performance for hyperscale data centre server, 5/6G infrastructure, DPU and edge-of-network markets.

X-FAB Group is set to receive subsidies as part of the new Important Project of Common European Interest in Microelectronics and Communication Technologies (IPCEI ME/CT).

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.