Search results for "chiplet"

The European ExaNoDe project has built a compute node prototype paving the way to exascale, combining 3DIC with multi-chip-module integration technologies, heterogeneous compute elements with Arm cores and FPGA acceleration and the UNIMEM memory system, all powered by a high-performance, high-productivity software stack.

The Cadence UltraLink D2D PHY IP from Cadence Design Systems is a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.

Rambus has announced the tapeout of its 112G XSR SerDes PHY on a 7nm process node optimised for PPA. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signalling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.

A team of Georgia Tech researchers is bringing electronic design software and communications expertise to DARPA's new CHIPS initiative, which will enable future generations of integrated circuits to be assembled from plug-and-play modules known as “chiplets.” Reusing blocks of existing microelectronics technology could reduce the need to design complex monolithic chips from scratch for new applications.

EUROSERVER, a leading EU-funded research project, is paving the way toward lower energy consumption in data centres. Based on the concept of chiplets, where multiple silicon subsystems are mounted in an integrated device, along with an associated new groundbreaking system architecture, the project has enabled more energy-efficient servers and has even inspired startups motivated by the new technology.

Leti has announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.