Search results for "TSMC"
Top 20 Semiconductor Suppliers’ Sales Growth Rates Forecast to Range from Great (+31%) to Terrible (-17%) in 2012.
A forecasted ranking and discussion of the 2012 top semiconductor suppliers will be included as part of IC Insights' upcoming November Update to The McClean Report. Also included in the November Update will be a listing of the top semiconductor industry capital spenders and a description of a “new” IC industry cycle model.
Cortus Releases the World’s Smallest 32-bit Microcontroller IP Core
Cortus releases the world’s smallest 32-bit microcontroller IP core – the APS1. The launch of the silicon efficient, low cost APS1 completes Cortus’ 2012 processor roadmap. The APS1 is ideal for simpler embedded applications with limited code and data memory requirements. It offers a cost-effective way to replace many existing 8 bit cores by offering improved power consumption and simpler software development.
TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure
Cadence Design Systems announced today that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms. The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.
Synopsys and TSMC Collaborate for 20nm Reference Flow
Synopsys today announced 20-nanometer (nm) process technology support for the TSMC 20nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20nm design rules and models.
TSMC Validates Cadence 3D-IC Technology for Its CoWoS Reference Flow
Cadence Design Systems announced today that TSMC has validated Cadence 3D-IC technology for its CoWoS (chip-on-wafer-on-substrate) Reference Flow with the development of a CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP.
Synopsys and TSMC Deliver 3D-IC Design Support
Synopsys today announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS (Chip on Wafer on Substrate) Reference Flow. The design flow is the result of the latest collaboration between the companies on 3D-IC integration technologies.
Yole Développement predicts 2x growth in the IPD market by 2017
Yole Développement has released its Thin-Film IPDs report, analysing the existing and upcoming technologies and applications for IPDs. The report describes the thin-film IPD market, growth opportunities and the associated technologies deep inside each application.
Mentor Graphics Provides Design, Verification and Test Solutions for TSMC's 20nm Design Infrastructure
Mentor Graphics today announced new capabilities to complement TSMC's 20nm manufacturing processes. Enhancements to support both digital and analog/mixed signal 20nm reference flows include new features in the PyxisT IC Station platform, the Eldo fast SPICE simulation products, the Olympus-SoCT place and route system, the CalibreR nmDRCT, Calibre RealTime, Calibre PERCT and Calibre xACT 3D solutions, and the TessentR silicon test product suite.
KALRAY Announces 1st samples of MPPA 256 processor in 28nm
KALRAY today announced the availability of first samples of the 28 nanometer MPPA 256 processor targeting embedded applications among them Imaging and signal processing. First products to be ramped in volume will be processors for signal processing in an imaging application. Product qualification is scheduled for completion in Nov 2012.
Open-Silicon selects Synopsys IC Compiler and achieves 1.3 GHz performance
IC Compiler is a cornerstone of the Synopsys Galaxy Implementation Platform, and its advanced optimization technologies, unique leakage power recovery capability and predictable flow with Synopsys Design Compiler Graphical synthesis solution were key contributors to Open-Silicon achieving the performance and power targets and predictable timing closure for the hardened processor core.