Search results for "TSMC"

Synopsys, Inc today announced TSMC's certification of Synopsys' Laker custom design solution for the TSMC 16-nanometer (nm) FinFET process Design Rule Manual (DRM) V0.5 as well as the availability of a 16-nm interoperable process design kit (iPDK) from TSMC. With its robust support for the iPDK standard, Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180-nm to 16-nm. Along with...

Customers in the Americas region (primarily the U.S.) are expected to account for nearly two-thirds of pure-play foundry sales in 2013, a slight increase from 2012. IC Insights forecasts that Americas region will represent 70% of TSMC’s sales, 67% of sales from GlobalFoundries, and 47% of sales from both UMC and SMIC (Figure 1).

IC Insights has published a list of the top semiconductor sales leaders for the first half of 2013. The list showed the usual big-time players that we’ve come to expect like Intel, Samsung, and TSMC, leading the way in semiconductor sales through the first six months of the year. What stood out nearly as much, however, was that only one Japanese company—Toshiba—was present among the top 10 suppliers through the first half of 201...

Altera Corporation and Micron Technology today announced they have jointly demonstrated successful interoperability between Altera Stratix V FPGAs and Micron’s Hybrid Memory Cube. This technology achievement enables system designers to evaluate today the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing designs. The demonstration provides an early proof point that production support of HMC...

Cadence Design Systems announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own cutting-edge IP. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers, creating and delivering fully qualified and high-quality native SKILL-based PDKs to enable all the leading-edge features of the Virtuoso platform.

Finding, identifying and fixing manufacturing defects and systemic yield limiters within library cells at 90nm and beyond. Stephen Pateras, product marketing director for Mentor Graphics Silicon Test product, explores Cell-Aware ATPG in this article from ES Design magazine.

IC Insights’ new 250-page Mid-Year Update to the 2013 McClean Report, describes why a very clear distinction should be made between the IC market (i.e., consumption) in China and IC production within China. Although China has been the largest individual market for ICs since 2005, it does not necessarily mean that large increases in IC production within China would immediately follow, or ever follow.

Sondrel has just completed its third 28nm design this year - for a leading communications company – and is closing on two more at this node. Although Sondrel has worked on over 200 IC designs at all nodes down to 20nm, and chip sizes over 700mm², the fact that the company has so many successful tape-outs at 28nm convinces CEO Graham Curren that 28nm will be the preferred geometry for complex chips for some time to come.

Cadence Design Systems announced today that several of its system-on-chip development tools have achieved version 0.1 of design rule manual and SPICE model tool certification for TSMC’s 16-nanometer FinFET process.

Synopsys announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16-nm FinFET process Design Rule Manual and SPICE V0.1. TSMC's certification is built on early collaboration for extraction and modeling of 3-D parasitics in FinFET devices and extends to full-line design implementation solutions.