Search results for "TSMC"

Xilinx and TSMC announced that they are teaming together to create the fastest time-to-market and highest performance FPGAs to be built on TSMC's 16-nanometer FinFET process, a program Xilinx calls 'FinFast.'

Mentor Graphics Corp today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60% compared to initial design kits released last year.

Cadence Design Systems announced today that TSMC has certified the new Cadence Tempus Timing Signoff Solution at 20 nanometers. The certification means the Cadence Tempus Timing Signoff Solution passes TSMC’s rigorous EDA tool certification to enable customers to achieve accuracy required for advanced technologies.

Energy Micro annonce ce jour avoir travaillé étroitement avec TSMC afin de vérifier les avantages du processus eLL (Extreme Low Leakage) du fondeur pour la fabrication de ses microcontrôleurs éco-énergétiques Cortex-M de prochaine génération. En se rapprochant étroitement de TSMC, Energy Micro a bénéficié d’un accès anticipé à sa technologie afin d’améliorer encore la performance de son portefeuille de MCU.

Energy Micro has revealed that it has been working closely with TSMC to verify the benefits of using the TSMC Extreme Low Leakage process to fabricate its next generation of energy efficient Cortex-M microcontrollers. By aligning closely with TSMC, Energy Micro has benefitted from early access to the process technology to further enhance its MCU portfolio.

At this week’s VLSI 2013 Technology Symposium 2013, imec presented important findings increasing the understanding into the stochastic nature of Resistive Random Access Memory (RRAM) operation. Imec’s results are crucial steps forward to enable reliable implementation of the memory concept.

At the VLSI 2013 symposium, imec presented the first strained Germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation. The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous FinFET/nanowire devices.

Altera Corporation vient de dévoiler ses FPGA et SoC (système-sur-puce) Generation 10, proposant aux développeurs système des niveaux révolutionnaires de performances et d’efficacité énergétique. Les composants Generation 10 sont basés sur une technologie de process et une architecture optimisée pour fournir les performances les plus élevées de l’industrie et les plus hauts niveaux d’intégration système pour la consommation la...

Altera today introduced its Generation 10 FPGAs and SoCs, offering system developers breakthrough levels of performance and power efficiencies. Generation 10 devices are optimized based on process technology and architecture to deliver the industry’s highest performance and highest levels of system integration at the lowest power.

Energy Micro a commencé à livrer ses microcontrôleurs Wonder Gecko, les plus récents et les plus avancés de la famille EFM32 et pour lesquels les composants et les kits de conception sont maintenant disponibles. L’EFM32 Wonder Gecko intègre le processeur ARM Cortex-M4, qui fournit un jeu d’instruction DSP complet et une unité à virgule flottante (FPU) dédiée. De plus, ce MCU utilise la technologie silicium eLL (extreme low leakage)...