Search results for "Synopsys"

Synopsys has announced Fuji Xerox used its ASIP Designer tool to design a high-performance Application-Specific Instruction Set Processor (ASIP) for its full-colour multifunction printer. With ASIP Designer, Fuji Xerox developed a specialised instruction-set custom processor that consumed less than 50% of the die area of a fixed hardware implementation while still meeting the performance requirements. In addition, unlike fixed hardware, an ASIP o...

A new ATPG and diagnostics technology that delivers 10X faster run time and 25 percent fewer test patterns has been introduced by Synopsys. It will shorten schedules, accelerate silicon debug and reduce test time and cost. Innovative, memory-efficient engines for test generation, fault simulation and diagnosis execute finely segmented threads on all available server cores, maximising throughput while minimising the number of patterns required to ...

TetraMAX ATPG, DesignWare STAR Hierarchical System and DesignWare STAR Memory System, key components of Synopsys' manufacturing test solution, are now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar, an independent accredited assessor, formally certified Synopsys' TetraMAX, STAR Hierarchical System and STAR Memory System following an in-depth Functional Safety Process Audit of the tool and IP development proce...

Synopsys has announced the industry's first security IP solutions compliant to the Secure Hash Algorithm-3 (SHA-3) cryptographic standard from the National Institute of Standards and Technology (NIST). Synopsys' DesignWare SHA-3 Cryptography IP solutions enable developers to protect the integrity of electronic information in applications such as message authentication and digital signatures, random number generation and key derivation functions. ...

Synopsys has announced the successful tape-out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10nm FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process.

Synopsys has announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10nm FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10nm process to realise the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015.

Synopsys will host a free one-day event focused on the latest technologies and trends in embedded processor IP, software and programming tools. In this dual-track event, experts from Synopsys, ecosystem partners and ARC processor users will describe how to overcome design challenges with hardware and software solutions optimised for low-power embedded applications. In addition, live demonstrations will showcase applications including IoT, embedde...

Synopsys has announced a comprehensive portfolio of IP optimised to address the security, wireless connectivity, energy-efficient and sensor processing requirements for a wide range of IoT applications such as wearables, smart appliances, metering and wireless sensor networks. The DesignWare IP portfolio for the IoT includes power- and area-efficient logic libraries, memory compilers, NVM, data converters, wired and wireless interface IP, securit...

Imagination Technologies announces that it is offering complete Ensigma connectivity IP system solutions including WiFi/Bluetooth software, Media Access Control (MAC) layer, baseband, AFE and RF, through a range of flexible licensing and support models.

TSMC has certified Synopsys' IC Compiler II place and route product for V0.9 of 10nm FinFET (N10FF) process technology and are on track to work towards V1.0 completion in Q4, 2015. IC Compiler II is the successor to IC Compiler, the place and route solution for advanced designs, delivering an improvement in throughput while achieving quality-of-results that meets TSMC's certification requirements.