Search results for "Synopsys"

Synopsys has announced the HAPS-80 FPGA-based prototyping systems, a part of its end-to-end prototyping solution. The HAPS-80 systems deliver up to 100MHz multi-FPGA performance and new proprietary High-Speed Time-Domain Multiplexing (HSTDM) technology.

Synopsys has announced availability of the DesignWare ARC EM9D and EM11D processors, the newest additions to the power-efficient ARC EM family of processors. The EM9D and EM11D cores implement an enhanced version of the ARCv2DSP instruction set architecture, combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimising power consumption. The cores maximise processing through...

Synopsys has announced that Renesas has deployed Synopsys' Design Compiler Graphical solution for their designs. Improving performance, while reducing power and area, is critical for Renesas to offer high performance balanced with very low power consumption over a wide and scalable range of products. To achieve these goals, Renesas deployed a design flow that combines Design Compiler Graphical and Synopsys' IC Compiler place-and-route solution.

Synopsys has announced the availability of DesignWare Logic Library and Embedded Memory IP for the Mie Fujitsu Semiconductor 40nm Low-Power (40LP) process. Designers using the Mie Fujitsu Semiconductor 40LP process can integrate DesignWare Logic Library and Embedded Memory IP to optimise the power efficiency and performance of their designs. The IP is made available through Synopsys' Foundry-Sponsored IP Program, which enables designers to licens...

The latest release of the company's comprehensive physical verification signoff product, IC Validator 2015.06, has been introduced by Synopsys. The 2015.06 release focuses on refinements to the core engines to deliver a two times memory footprint reduction and 20% faster signoff design rule check performance on average. Twice as fast in many cases, IC Validator 2015.06 allows designers to extend the use of their current workstations and manage mu...

Synopsys' IC Validator used advanced multi-processing techniques to speed up the Design Rule Checking (DRC) of Mellanox's latest design. IC Validator completed the signoff physical verification using TSMC's 28nm signoff runset and reduced the DRC elapsed time for this large design to under 14 hours by automatically distributing the job over 28 processor cores.

Synopsys has announced that students from the University of Rochester and University of Arizona received awards for their entries in the 2015 Robert S. Hilbert Memorial Optical Design Competition. The annual competition is open to students in North America working toward a bachelor's, master's or doctorate degree who utilise Synopsys' CODEV or LightTools software to perform optical design and engineering research. The awards are granted to studen...

A PCI Express (PCIe) protocol exerciser/analyser for testing PCI Express 4.0 designs and products has been introduced by Teledyne LeCroy. The Summit Z416 exerciser/analyser addresses the needs of PCI Express developers by providing high performance 16GT/s traffic generation on devices with link widths up to 16 lanes. In addition to traffic generation, protocol analysis featuring Teledyne LeCroy’s industry-standard CATC Trace and other traff...

FPT Software, a large global technology, outsourcing and IT services company headquartered in Vietnam, has adopted Coverity Enterprise Code Advisor, Synopsys' static code analysis solution, to help ensure their client deliverables meet the highest quality and security standards.

Synopsys has completed its acquisition of Atrenta, a provider of SoC realisation solutions for the semiconductor and consumer electronics industries. Atrenta is a recognised leader in static and formal technologies and the acquisition supports Synopsys' strategy to quickly and effectively deliver the advanced capabilities that will help semiconductor customers solve their toughest design and verification challenges.