Search results for "TSMC"

Technologies for the next stage of wearable device development. By Laurence Bryant, VP of Strategic Marketing, ARM.

Semiconductor industry capital expenditures in 2015 are expected to be $69bn in 2015, up 6% from $65bn in 2014, according to IC Insights. Semiconductor Intelligence has compiled a 2015capital expenditureoutlook by company. The major memory companies account for 38% of 2015capital expenditureand the major foundries account for 27%.

Cadence Design Systems has announced that its digital and custom/analogue tools have achieved certification from TSMC for its most current version of 10nm FinFET Design Rule Manual (DRM) and SPICE models.The custom/analogue and digital implementation and signoff tools have been certified by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure on the 10nm FinFET process.

To enable designers to integrate required functionality in mobile and enterprise SoCs with less risk, Synopsys has introduced a portfolio of DesignWare PHY IP for TSMC's 16nm FinFET Plus (16FF+) processes. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCIe 4.0, 3.0 and 2.0; SATA ...

An UBM-free WLCSP technology that provides enhanced quality, reliability and integration for Altera’s MAX 10 FPGA products has been developed by Altera and TSMC. This approach results in a thin package height of less than 0.5mm (including solder ball), which is suitable for applications where space is at a premium.

Synopsys has announced that TSMC has concluded 16nm FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys' custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys' Galaxy Design Platform for 16nm production designs and 10nm early engagements.

The growing popularity of smartphone and DTV applications with 4K displays translates into demand for next-gen portable displays featuring high resolution and excellent power performance. The TSMC 55nm HV process provides an efficient infrastructure to design cost-effective and low-power display drivers.

Mentor Graphics has announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification.Calibre physical verification and Design For Manufacturing (DFM) platform, and theAnalog FastSPICE (AFS) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.

Semtech has announced a collaboration with MorethanIP, linking the IP from each party to produce a complete layer 1/layer 2 solution for IEEE 802.3bj, the recently ratified standard supporting 100G backplane applications.

More than any other industry, the semiconductor business is defined by rapid technological change. As a result, a constant and high level of investment in R&D is essential to the competitive positions of semiconductor suppliers. The figure below shows IC Insights’ 2014 ranking of semiconductor companies by R&D spending.