Search results for "TSMC"

Imagination Technologiesand TSMC have announced a collaboration to develop a series of advanced IP subsystems for the IOT, to accelerate time to market and simplify the design process for mutual customers. These IP platforms, complemented by highly optimised reference design flows, bring together the breadth of Imagination’s IP with TSMC’s advanced process technologies from 55 down to 10nm.

Synopsys has announced TSMC's certification of the IC Compiler II place and route solution on TSMC's 16nm FinFET Plus (16FF+) process. The IC Compiler II is the successor to IC Compiler, the industry's widely adopted place and route solution for advanced designs at both established and emerging nodes.

Synopsys and TSMC are collaborating to develop an integrated IoT platform on TSMC's 40nm ultra low power process technology. The platform incorporates a broad range of DesignWare IP, including an integrated sensor and control IP subsystem with the ultra low power ARC EM5D processor core, power- and area-optimised logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an ADC.

IC Insights will release an update to the 2015McClean Reportin late May 2015. Thisupdateincludes a discussion of the history and evolution of IC industry cycles, an update of the capital spending forecast by company, and a look at the top 25 1Q15 semiconductor suppliers (the top 20 1Q15 semiconductor suppliers are covered in this bulletin).

To enable the fast and efficient development of highly customised chips for smart connect devices, ARM has announced its latest hardware subsystem. The ARM IoT subsystem for ARM Cortex-M processors is optimised for use with ARM's most efficient processor and radio technologies, physical IP and ARM mbed OS.

Fan-out wafer level packaging is now entering a new era. With a high expected growth of the market, multiple new companies, OSATs and even foundries are involved in this platform. According to Yole Développement’s Fan-Out and Embedded Die: Technologies & Market Trends and Equipment & Materials for 3DIC & Wafer-Level Packaging Applications reports, the market reached more than $150m in 2014 and a CAGR of 30% for the next 5...

Targeting applications requiring a high level of processing per MHz and low power consumption in a small footprint, the the eSI-32X0MP scalable, asymmetric multicore processor has been released by EnSilica. The processor, which expands the company’s eSi-RISC family, is suitable for WiFi, LTE Cat-0 and other IoT standards as well as scalable sensor, Gbit security protocol and solid state disk levelling algorithm processing.

MediaTek has announced the launch of the MediaTek Helio P10, a high-performance, high-value SoC focused on the growing demand for slim form-factor smart phones that provide premium, flagship features. The Helio P10 showcases a 2GHz, True Octa-core 64-bit Cortex-A53 CPU and a 700MHz, Dual-core 64-bit Mali-T860 GPU. The Helio P10 will be available Q3 2015 and in consumer products by late 2015.

The USB 3.0 host IP solution for TSMC’s 16nm FinFET Plus (16FF+) process is one of the first to pass USB-IF compliance testing and receive USB-IF certification, maker Cadence has announced. The complete controller and PHY integrated solution is pre-verified, which enables designers to mitigate project risk and reduce SoC integration and verification time.

During the IEEE IITC conference in Grenoble, nanoelectronics research centre imec and Lam Research jointly presented a bottom-up prefill technique for vias and contacts. The technique, based on ElectroLess Deposition (ELD) of cobalt, is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic...