Search results for "TSMC"

Larger wafer diameters provide more chips per wafer at a modest increase in material and process costs, resulting in reduced chip costs. Historically, transitions to larger diameter wafers have provided cost reductions greater than 20% per unit area. However, enormous financial and technology hurdles continue to plague the development of, and the transition to, 450mm wafers.

In a competitive landscape, Yole Développement points out the serenity of the Wide Band Gap (WBG) market and the confidence of its players: WBG companies are slowly but surely reshaping the industry and accelerate the market adoption with numerous strategic mergers and acquisitions (Cree, Infineon Technologies…) and the development of disruptive solutions.In its latest technology and market analysis, 'GaN & SiC for power electro...

Synopsys' IC Validator used advanced multi-processing techniques to speed up the Design Rule Checking (DRC) of Mellanox's latest design. IC Validator completed the signoff physical verification using TSMC's 28nm signoff runset and reduced the DRC elapsed time for this large design to under 14 hours by automatically distributing the job over 28 processor cores.

According to IC Insights, the pure-play foundry market is forecast to grow to an all-time high of $12.2bn in 4Q15, following several quarters in which sales remained between $11.3 and $11.8bn, see (Figure 1). IC Insights defines a pure-play foundry as a company that does not offer a significant amount of IC products of its own design but instead focuses on producing ICs for other companies, such as TSMC, GlobalFoundries, UMC and SMIC.

In partnership with TSMC, Dolphin Integration has developed all the IP contributors for an ultra-low-power SoC suitable for IoT applications. Extreme power consumption reduction of an SoC requires a power domain architecture, which is a complex task for SoC integrators. Therefore, more semiconductor IPs are necessary than usual to enable the performance needed for SoC differentiation in competitive markets.

Synopsys has achieved certification and compliance from multiple standard organisations for a broad range of DesignWareIP on the TSMC 16-nm FinFET Plus (16FF+) process includingUSB 2.0 and USB 3.0,PCI Express3.1,HDMI2.0,MIPID-PHYand SATA IP solutions.By achieving certification of its DesignWare IP, Synopsys gives designers confidence that the IP is interoperable and functions as expected in the TSMC 16FF+ process.

At SEMICON West, imec and SPTS Technologies announced that they are jointly developing a highly accurate, short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.

Cadence Design Systems has announced that it is collaborating with TSMC on the development of an IoT IP subsystem demonstration platform for TSMC’s Ultra-Low Power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analogue tools, provides the opportunity to simplify IoT designs and accelerate the time-to-market for...

A stereo audio CODEC supporting both analogue and digital microphones has been introduced by Dolphin Integration. The sCODa-MT1-LR.01 is suitable for SoCs targeting wireless audio devices, such as Bluetooth speakers or sound bars, where sound performance and die cost are pivotal.

Cadence Design Systems has announced that Cadence Innovus Implementation System has achieved v1.0 Design Rule Manual (DRM) certification from TSMC for its 16nm FinFET Plus (16FF+) process. The Innovus Implementation System successfully passed rigorous testing and has been validated by TSMC on high-performance reference designs in order to provide customers with a fast path to design closure.