Search results for "tsmc"

Cadence Design Systems has announced a broad IP portfolio for TSMC’s 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio and is actively engaged with customers as adoption of TSMC’s leading-edge process grows. The initial deliveries of Cadence IP for the N10 process demonstrate a 20% power reduction and 50% area reduction compared to TSMC’s 16nm process technology and are suitable for ...

Cadence Design Systems has announced that its digital, custom/analogue and signoff tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve V1.0 completion by Q4 2015. The certification enables system and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high-end servers.

The total pure-play foundry market is forecast to grow 6.1% to $44.9bn in 2015. The entire increase in pure-play foundry sales is forecast to be due to sales of devices built using leading edge (less than 40nm) feature sizes. The <40nm pure-play foundry market is expected to increase 24% to $16.1bn in 2015 compared to $13.0bn in 2014 (see Figure 1, below). In contrast, pure-play foundry sales of ≥40nm devices are forecast to decline 2% to $...

Synopsys has announced the successful tape-out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10nm FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process.

Synopsys has announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10nm FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10nm process to realise the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015.

Cadence Design Systems has announced that its Cadence Innovus implementation system has achieved V0.9 certification for TSMC’s 10nm FinFET process and is currently on track to complete V1.0 in Q4 2015. The Innovus implementation system is a next-gen physical implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-performance reference designs, providing customers with a fast path to implemen...

Synopsys has announced a comprehensive portfolio of IP optimised to address the security, wireless connectivity, energy-efficient and sensor processing requirements for a wide range of IoT applications such as wearables, smart appliances, metering and wireless sensor networks. The DesignWare IP portfolio for the IoT includes power- and area-efficient logic libraries, memory compilers, NVM, data converters, wired and wireless interface IP, securit...

Cadence Design Systems has announced that its Allegro System-in-Package (SiP) and Physical Verification System (PVS) implementation technologies have been enabled for TSMC’s Integrated Fan-Out (InFO) packaging technology. By providing an integrated solution that automates the Design-Rule Checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.

TSMC has certified Synopsys' IC Compiler II place and route product for V0.9 of 10nm FinFET (N10FF) process technology and are on track to work towards V1.0 completion in Q4, 2015. IC Compiler II is the successor to IC Compiler, the place and route solution for advanced designs, delivering an improvement in throughput while achieving quality-of-results that meets TSMC's certification requirements.

Larger wafer diameters provide more chips per wafer at a modest increase in material and process costs, resulting in reduced chip costs. Historically, transitions to larger diameter wafers have provided cost reductions greater than 20% per unit area. However, enormous financial and technology hurdles continue to plague the development of, and the transition to, 450mm wafers.