Search results for "tsmc"

Magma Design Automation announced immediate availability of the Titan Analog Design Kit for TSMC 180-nanometer (nm) and 65-nm processes, that implements Titan’s model-based design methodology with Titan FlexCells, which are modular, process- and specification-independent, reusable analog building blocks. The kit provides an analog design ecosystem that enables mutual Magma and TSMC customers to dramatically improve design quality and designer p...

At this week’s VLSI Technology Symposium (Honolulu, Hawaii, USA), imec presents significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and imec introduces a new modeling approach increasing the fundamental understanding of RRAM process technology.

In the effort to enhance the advanced metal-high-k gate stack for next-generation logic devices, imec successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200x-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric.

W. L. Gore & Associates is offering a new family of highly efficient cartridge filters that improve water quality and reduce total cost of filtration for ultrapure water (UPW) and de-ionized (DI) water used in the manufacture of semiconductors and silicon wafers.

Cadence Design Systems, Inc. today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals and SPICE models.

Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today announced that TSMC has selected Quartz DRC and Quartz LVS for physical verification in TSMC’s Integrated Sign-off Flow (ISF). TSMC provides certified flow comprising proven, best-in-class tools to enable the fastest path to TSMC silicon. The flow is now available for 65-nanometer (nm) designs.

At the International Electron Devices Meeting in San Francisco imec’s advanced CMOS research program reports promising advances in scaling logic, DRAM and non-volatile memory. A new device based on non-silicon channels was realized to scale high-performance logic towards the sub-20nm node. Moreover, imec developed low-leakage capacitors allowing DRAM to be pushed to the 2x nm node. And the switching mechanism of resistive RAM for next-generatio...

Imec sets major step towards 20nm half pitch interconnects with the realization of electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning approach.