Search results for "tsmc"
PowerVR graphics boost MediaTek’s Helio X30 chipset
Imagination Technologies announces that MediaTek selected its PowerVR Series7XT Plus GPU to achieve higher performance and lower power graphics in its new flagship MediaTek Helio X30 processor. The full-featured 10-core Helio X30 is MediaTek’s most advanced smartphone chipset to-date, with graphics that achieve a 2.4x performance boost and power savings up to 60 percent compared to the previous generations.
Extend the operation time of your battery powered SoC
Allowing devices to run on the same battery for years rather than months significantlyenhances end-user satisfaction. Numerous wireless communication SoC, whether BLE, Zigbee, Sigfox, LoRa or M2M 4G, have a duty cycle such that the power consumption in sleep mode dominates the overall current drawn from the battery.
China’s MIC 2025 results for ICs predicted to fall short
The newly released 20thanniversary edition ofThe McClean Reportcontains an analysis of the three phases of China’s attempt to gain a stronger presence in the IC industry (Figure 1). The analysis of phase three includes a long list of the successes and setbacks that the Chinese have faced since initiating this strategy in 2014.
Enabling verification tools for InFO Tech variants
Mentor Graphics announced that TSMC has extended its collaboration with Mentor Graphics on the Xpedition Enterprise platform in conjunction with the Calibre platform for the design and verification of TSMC’s InFO (Integrated Fan-Out) packaging technology for multi-chip and chip-DRAM integration applications. Mentor developed new Xpedition functionality specifically to support InFO and enable the IC package designer to complete design tasks ...
The IP landscape of advanced fan-out packaging
In today's fast-growing fan-out market showing an 80% increase between 2015 and 2017, it is essential to deeply understand the patent strategies of the key players. The Technology Intelligence and IP Strategy Company, KnowMade, has thoroughly investigated the fan-out packaging patent landscape and has released a patent landscape analysis entitledFan-Out Wafer Level Packaging.
3D-Compatible Germanium nMOS Gate stack has high mobility
At this week’s IEEE IEDM conference, imec, the world-leading research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI).
Espressif licenses CEVA Bluetooth in ESP32 IoT chip
CEVA announced Espressif Systems, a leading fabless semiconductor company providing low power wireless solutions for the IoT applications has licensed and deployed the RivieraWaves Bluetooth dual mode technology in its new ESP32 chip.Espressif Systems, with headquarters in Shanghai, is focused on creating innovative, versatile solutions to enable low cost wireless connectivity in a wide range of products.
2016 semiconductor capex at its highest in 5 years
Global semiconductor capital expenditures (capex) are expected to return to the level of 2011 either this year or next. 2011 was the record year for capex as the industry returned to growth following the 2009-2010 recession.
Five top-20 semiconductor suppliers to show double-digit gains in 2016
IC Insights will release its November Update to the 2016 McClean Report later this month and will release its 20th anniversary edition of The McClean Report in January of next year. The November Update includes the latest semiconductor industry capital spending forecast, a detailed forecast of the IC industry by product type through 2020, and a look at the top-25 semiconductor suppliers expected for 2016. The top-20 2016 semiconductor suppliers a...
SoC Fabric for IoT from Dolphin Integration
Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing with noise issues in a mixed-signal SoC embedding multiple power domains with diverse power modes.