Search results for "tsmc"

New process improvements for next-gen devices were unveiled by imec at 2017Symposia on VLSI Technology and Circuits. For the first time, scaled strained germanium p-channel Gate-All-Around (GAA) FETs were shown with sub-10nm diameter, integrated on a 300mm platform. In addition, the research centre has obtained a significant improvement in device performance and electrostatic control with high-pressure anneal (HPA) for both strained germanium p-c...

Imec has announced at the 2017 Symposia on VLSI Technology and Circuits the world’s first demonstration of a vertically stacked ferroelectric Al doped HfO2 device for NAND applications. Using a new material and a novel architecture, imec has created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention.

At this week’s 2017 Symposia on VLSI Technology and Circuits taking place in Japan, imec, the research and innovation hub in nano-electronics and digital technology, reported record breaking values below 10-9Ω/cm2for PMOS source/drain contact resistivity. These results were obtained through shallow Gallium implantation on p-SiliconGermanium (p-SiGe) source/drain contacts with subsequent pulsed nanosecond laser anneal.

EnSilica and sureCore have announced that EnSilica has developed sureCore’s new, ultra-low power IoT reference platform targeted principally at the development of the next generation of wearable consumer and medical applications.With proven expertise in low power SoC design for battery powered applications, EnSilica’s experienced silicon team is able to deliver a complete, turn-key service covering complex digital and analog/RF techno...

VOICE, the annual developer conference hosted by semiconductor test equipment supplier Advantest will kick off its second decade with 113 technical presentations, an expanded Technology Kiosk Showcase, and a new technology track. Additionally, VOICE 2017 will include three diverse keynote speakers, a Partners’ Expo, and interactive discussion sessions for users of the V93000 and T2000 SoC test platformsas well as Advantest test cell solutio...

Mentor Graphics has announced that TSMC has certified the Calibre Platform (Calibre nmDRC, Calibre Multi-Patterning, Calibre nmLVS, Calibre YieldEnhancer with SmartFill, and Calibre xACT tools), as well as the Analog FastSPICE (AFS) Circuit Verification Platform, for the most current version of the 12FFC process.

It requires true differentiating factors when launching any low-power SoC on a highly competitive market. For IoT applications requiring ultra-low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimise power modes by partitioning the SoC.

As the development of packaging technologies intensifies, in order to accommodate further front-end scaling trends and multi-die integration, advanced FO RDL and FC substrates represent the key interconnect components. The competition between FO and FC packages and the features of their interconnect components is resulting in an abundance of new package architectures that are crucial in enabling future products and markets.

New optimisation capabilities have been announced within Cadence Design Systems' holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The integrated flow provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications.

VOICE, the annual developer conference hosted by leading semiconductor test equipment supplier Advantest will offer three diverse keynote addresses ranging from future trends to cyber security to the global semiconductor industry.