Search results for "tsmc"

Sondrel has announced the tape-out of its largest chip design for a customer. This has taken a team of up to 200 engineers working on it simultaneously at times to design the 500 square millimetre chip that has over 30 billion transistors, 40 million flipflops, and 23 thousand pads for I/O, power and ground.

Cadence Design Systems has announced the certification of the Cadence tools in TSMC reference flows for TSMC’s latest InFO and CoWoS advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS-S).

Cadence Design Systems has announced that its digital full flow and custom tool suite has been optimised for TSMC’s 3nm (N3) process technology. The Cadence tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for TSMC’s N3 process.

Cadence Design Systems has announced the availability of its silicon-proven Cadence UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the TSMC N7 process with full silicon characterisation data is now available, for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed.

IC Insights recently released it August Update to the 2020 McClean Report that included the first of a two-part analysis on the global IC foundry market. IC Insights defines a pure-play foundry as a company that does not offer a significant amount of IC products of its own design, but instead focuses on producing ICs for other companies.

CEVA has announced support for Dolby MS12 Multistream Decoder for the CEVA-BX2 audio DSP. As smart TVs, over-the-top (OTT) content services and set-top-boxes evolve into multipurpose digital media receivers, the content is derived from numerous sources, utilising a variety of audio codecs.

Rambus has announced it has achieved a 4Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry’s fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device.

NXP Semiconductors and TSMC have announced a collaboration agreement to adoptTSMC 5nm process technology for NXP’s next generation, high-performance automotive platform. This collaboration combines NXP’s automotive design expertise with TSMC’s industry-leading 5nm technology to further drive the transformation of automobiles into powerful computing systems for the road.

Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.

Synopsys has announced certification of its digital and custom design platforms for TSMC's N5 and N6 process technologies. Synopsys' long-term collaboration with TSMC has resulted inacceleratingnext-generation product design for key vertical markets, including high-performance computing (HPC), mobile, 5G, and AI chip designs.