Synopsys has announced the industry's first demonstration of MIPI D-PHY IP on TSMC's 16FF+ (16nm FinFET Plus) process operating at 2.5Gb/s per lane. The demonstration shows the DesignWare D-PHY receiver lane connected to Keysight Technologies' test equipment, which provided burst-mode stimulus for stressed eye testing and the transmitter lane connected to the Keysight oscilloscope displaying the transmitter's performance.

Featuring multiprocessing technology that accelerates runtime by up to three times compared to the previous-gen and physically-aware advanced synthesis to increase timing quality of results by up to 10%, Synopsys has announced the latest release of the its Synplify Pro and Synplify Premier FPGA synthesis software tools.

A new ATPG and diagnostics technology that delivers 10X faster run time and 25 percent fewer test patterns has been introduced by Synopsys. It will shorten schedules, accelerate silicon debug and reduce test time and cost. Innovative, memory-efficient engines for test generation, fault simulation and diagnosis execute finely segmented threads on all available server cores, maximising throughput while minimising the number of patterns required to ...

TetraMAX ATPG, DesignWare STAR Hierarchical System and DesignWare STAR Memory System, key components of Synopsys' manufacturing test solution, are now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar, an independent accredited assessor, formally certified Synopsys' TetraMAX, STAR Hierarchical System and STAR Memory System following an in-depth Functional Safety Process Audit of the tool and IP development proce...

Synopsys has announced Fuji Xerox used its ASIP Designer tool to design a high-performance Application-Specific Instruction Set Processor (ASIP) for its full-colour multifunction printer. With ASIP Designer, Fuji Xerox developed a specialised instruction-set custom processor that consumed less than 50% of the die area of a fixed hardware implementation while still meeting the performance requirements. In addition, unlike fixed hardware, an ASIP o...

Synopsys has announced the industry's first security IP solutions compliant to the Secure Hash Algorithm-3 (SHA-3) cryptographic standard from the National Institute of Standards and Technology (NIST). Synopsys' DesignWare SHA-3 Cryptography IP solutions enable developers to protect the integrity of electronic information in applications such as message authentication and digital signatures, random number generation and key derivation functions. ...

Synopsys has announced a comprehensive portfolio of IP optimised to address the security, wireless connectivity, energy-efficient and sensor processing requirements for a wide range of IoT applications such as wearables, smart appliances, metering and wireless sensor networks. The DesignWare IP portfolio for the IoT includes power- and area-efficient logic libraries, memory compilers, NVM, data converters, wired and wireless interface IP, securit...

Synopsys has announced the successful tape-out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10nm FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process. 

Synopsys has announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10nm FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10nm process to realise the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015.

TSMC has certified Synopsys' IC Compiler II place and route product for V0.9 of 10nm FinFET (N10FF) process technology and are on track to work towards V1.0 completion in Q4, 2015. IC Compiler II is the successor to IC Compiler, the place and route solution for advanced designs, delivering an improvement in throughput while achieving quality-of-results that meets TSMC's certification requirements.

Synopsys has announced the HAPS-80 FPGA-based prototyping systems, a part of its end-to-end prototyping solution. The HAPS-80 systems deliver up to 100MHz multi-FPGA performance and new proprietary High-Speed Time-Domain Multiplexing (HSTDM) technology. 

Synopsys will host a free one-day event focused on the latest technologies and trends in embedded processor IP, software and programming tools. In this dual-track event, experts from Synopsys, ecosystem partners and ARC processor users will describe how to overcome design challenges with hardware and software solutions optimised for low-power embedded applications. In addition, live demonstrations will showcase applications including IoT, embedde...

Synopsys has announced availability of the DesignWare ARC EM9D and EM11D processors, the newest additions to the power-efficient ARC EM family of processors. The EM9D and EM11D cores implement an enhanced version of the ARCv2DSP instruction set architecture, combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimising power consumption. The cores maximise processing through...

Synopsys has announced that Renesas has deployed Synopsys' Design Compiler Graphical solution for their designs. Improving performance, while reducing power and area, is critical for Renesas to offer high performance balanced with very low power consumption over a wide and scalable range of products. To achieve these goals, Renesas deployed a design flow that combines Design Compiler Graphical and Synopsys' IC Compiler place-and-route solution.

Synopsys has announced the availability of DesignWare Logic Library and Embedded Memory IP for the Mie Fujitsu Semiconductor 40nm Low-Power (40LP) process. Designers using the Mie Fujitsu Semiconductor 40LP process can integrate DesignWare Logic Library and Embedded Memory IP to optimise the power efficiency and performance of their designs. The IP is made available through Synopsys' Foundry-Sponsored IP Program, which enables designers to licens...

The latest release of the company's comprehensive physical verification signoff product, IC Validator 2015.06, has been introduced by Synopsys. The 2015.06 release focuses on refinements to the core engines to deliver a two times memory footprint reduction and 20% faster signoff design rule check performance on average. Twice as fast in many cases, IC Validator 2015.06 allows designers to extend the use of their current workstations and manage mu...

Synopsys' IC Validator used advanced multi-processing techniques to speed up the Design Rule Checking (DRC) of Mellanox's latest design. IC Validator completed the signoff physical verification using TSMC's 28nm signoff runset and reduced the DRC elapsed time for this large design to under 14 hours by automatically distributing the job over 28 processor cores.

Synopsys has announced that students from the University of Rochester and University of Arizona received awards for their entries in the 2015 Robert S. Hilbert Memorial Optical Design Competition. The annual competition is open to students in North America working toward a bachelor's, master's or doctorate degree who utilise Synopsys' CODE V or LightTools software to perform optical design and engineering research. The awards are granted to ...

FPT Software, a large global technology, outsourcing and IT services company headquartered in Vietnam, has adopted Coverity Enterprise Code Advisor, Synopsys' static code analysis solution, to help ensure their client deliverables meet the highest quality and security standards.

Synopsys has completed its acquisition of Atrenta, a provider of SoC realisation solutions for the semiconductor and consumer electronics industries. Atrenta is a recognised leader in static and formal technologies and the acquisition supports Synopsys' strategy to quickly and effectively deliver the advanced capabilities that will help semiconductor customers solve their toughest design and verification challenges.