Synopsys announces what is claimed to as the industry's first VIP to support the SAS (Serial-attached SCSI) 24G standard, making it the first VIP product line to support all SAS interface speed configurations. With increasing demands for the storage, backup and transmission of data, enterprise storage systems are challenged to rapidly transmit data across devices. Synopsys VC VIP for SAS delivers a comprehensive VIP solution, enabling SoC teams t...

Synopsys has announced the DesignWare Smart Data Fusion IP Subsystem, an integrated, pre-verified hardware and software IP product optimised for highly efficient DSP performance and ultra-low energy consumption. The Smart Data Fusion IP Subsystem offers a choice of DesignWare ARC EM DSP processors, including the latest EM9D and EM11D cores with support for XY memory to boost signal processing performance.

Synopsys has introduced the DesignWare USB-C 3.1/DisplayPort 1.3 IP solution which integrates USB Type-C (USB-C), SuperSpeed USB 10Gb/s (USB 3.1 Gen 2) and DisplayPort 1.3 interfaces with High-bandwidth Digital Content Protection (HDCP) 2.2 IP. The solution accelerates development of mobile and digital office SoCs that require 10Gb/s data transfer and delivery of secure audio/video content and power through a single USB Type-C connector.

The 2015.12 release of Synopsys' StarRC solution delivers key technology innovations to address the increasing parasitic extraction and signoff challenges arising from Moore's Law scaling continuation. The new innovations significantly raise the bar on performance and scalability, while providing an improved architecture designed to leverage mainstream or leading-edge compute resources more efficiently.

Synopsys has announced that its Platform Architect with MultiCore Optimisation (MCO) virtual prototyping solution is the first to support the IEEE 1801-2015 UPF (Unified Power Format) 3.0 system-level IP power modelling standard. The new standard enables efficient creation and reuse of interoperable IP power models for early analysis of power and performance for multicore SoC architectures.

The SiliconSmart ADV comprehensive standard cell library characterisation and QA solution has been released by Synopsys. SiliconSmart is tuned to produce sign-off quality PrimeTime libraries and provide maximum throughput on available compute resources.

Synopsys has announced that SK Hynix has achieved first-pass silicon success for its 64GB Universal Flash Storage (UFS) 2.0 device using Synopsys' DesignWare UFS Host Controller, UniPro Host Controller and M-PHY IP. By integrating Synopsys' high-quality, silicon-proven DesignWare IP, SK Hynix was able to accelerate their time-to-volume production by six months.

Synopsys has announced the release of Coverity 8.0, the latest version of the company's automated static analysis solution for addressing critical security vulnerabilities and quality defects in the source code of software. The Coverity 8.0 release includes several significant updates, including support for new programming languages, enhanced security testing capabilities and additional integration support for a number of development tools and en...

Synopsys has acquired Goanna Software. This acquisition provides Synopsys' Software Integrity Group with additional talent, technology and products that expand the company's presence in the emerging software quality and security market, support its vision of bringing a rigorous software sign-off process to software development, as well as increase its presence in Australia and the broader APAC region.

iCatch Technology has selected Synopsys' portfolio of DesignWare IP, scalable FPGA-based prototyping system and trusted professional design services for its digital video and image SoC. They adopted the silicon-proven DesignWare USB 2.0 picoPHY, Gen 2 DDR multiPHY and controllers, HDMI 2.0 TX PHY, data converter and audio analogue codec IP.

Axell, a fabless design company of graphics chips for interactive entertainment and industrial embedded systems, has switched to Synopsys' Design Compiler RTL synthesis solution for their IC designs. Achieving smaller die area with high engineering productivity are critical goals for Axell to deliver competitive products to their target markets. To achieve these goals, Axell evaluated available RTL synthesis solutions and selected the Design Comp...

Synopsys has announced the release of its CODE V version 10.8 software application for the design of imaging optical systems. This release supports the design of high-performance asymmetric and freeform optical systems with algorithmic enhancements that yield highly accurate computations of optical system parameters and enable precise control of those parameters during design optimisation.

Synopsys has announced version 2015.12 of the Synopsys RSoft Photonic System Design Suite, which includes new features to accelerate the design and fabrication of state-of-the-art silicon photonics, photonic ICs and optical transceivers in data centre applications. Also announced, version 2015.06-2 of the RSoft Photonic Component Design Suite enables faster simulations of complex photonic component designs with new, flexible cluster licensing pol...

A new verification IP (VIP) and source code test suite has been introduced by Synopsys to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard.

Synopsys announces the availability of advanced system-level capabilities in its next-gen VC Verification IP (VIP) for the ARM AMBA 4 ACE and AMBA 5 CHI protocols, as well as availability of verification IP for the recently announced AMBA 5 AHB5 protocol. The AMBA 4 ACE specifications are used for full coherency between processors and AMBA 5 CHI is an architecture for system scalability in enterprise SoCs.

Synopsys has announced the extension of a multi-year licensing agreement with ARM to provide the latest ARM Fast Models for ARM Cortex processors, including the recently announced ARM Cortex-A35 core, as part of Synopsys Virtualiser Development Kits. Synopsys VDKs are software development kits using virtual prototypes as the embedded target.

A collaboration between GLOBALFOUNDRIES and Synopses has resulted in a RTL-to-GDSII solution for the industry's first 22-nanometre (nm) fully depleted silicon-on-insulator (FD-SOI) technology process.

To expand its presence in the software quality and security market, Synopsys has acquired Canadian software company Protecode, which provides solutions for detecting and managing open source software (OSS) and the associated license and security risks.

Synopsys has announced availability of the Enhanced Security Package, a new licensable option for DesignWare ARC EM Processors. This ARC EM option enables designers to create an isolated, secure environment that protects their systems and software from evolving security threats such as IP theft and remote attacks. The Enhanced Security Package integrates Synopsys SecureShield technology, which provides support for separating secure and non-secure...

Since its introduction in 2014, Synopsys' IC Compiler II place and route system has been successfully deployed on more than 100 production designs, including more than 50 unique customers across 18 different foundry process nodes. This game-changing successor to IC Compiler, the industry's leading place and route solution, has enabled first-pass silicon success on dozens of these production designs ranging from 130 to the latest 10nm process node...