Synopsys has announced a suite of features for its 3200 Mbps DesignWare DDR4 IP to expand memory capacity for high-performance cloud computing systems while improving reliability, accessibility and serviceability (RAS). The DDR IP supports advanced error correcting code (ECC), which can correct all DRAM failures within a device to enable replacement of defective DIMMs without data loss.

Synopsys has announced the availability of key technology required by AEH SoC teams for compliance with the DO-254 standard. The DO-254 standard is used to ensure the highest level of safety in AEH designs for airborne applications. vBuilt upon the industry's leading Synopsys SpyGlass RTL Signoff solution, Synopsys' key technology includes a comprehensive set of necessary RTL and CDC checks, related methodologies and documentation to accelerate R...

Synopsys has announced that it was selected by NXP Semiconductor as its primary system-on-chip (SoC) verification solution for automotive and secure connectivity applications. Synopsys' comprehensive verification solution will be of primary use for the entire SoC verification cycle, including simulation, debug, formal verification, static verification, verification IP, emulation, and verification coverage. Synopsys' leadership position in all of ...

Synopsys has announced the DesignWare EV6x family, its latest generation of processor cores optimised for embedded vision applications requiring high definition resolutions. The fully programmable and configurable EV61, EV62 and EV64 embedded vision processors integrate one, two or four vision CPU cores and a programmable convolution neural network (CNN) engine.

To increase the speed of the SoC design process, Avnet ASIC Israel (AAI), a provider of system-on-chip (SoC) design, layout and manufacturing services, has selected the Synopsys Design Compiler Graphical RTL synthesis solution.

Synopsys has announced that early collaboration with ARM on its ARM Cortex-A73 CPU and ARM Mali-G71 GPU, targeted at a premium mobile experience, has resulted in successful early adopter tape-outs in advanced FinFET process technologies. The collaboration also delivered a Reference Implementation (RI) for Cortex-A73 with ARM Artisan standard cells, memories and ARM POP IP.

Synopsys has announced the addition of new models of Bosch timer and in-car communication IP for GTM, M_CAN and ERAY peripherals in its Virtualizer Development Kits (VDKs). VDKs are software development kits using a virtual prototype as the embedded target to enable software development, integration and test months before physical hardware is available.

Synopsys has announced the availability of the industry's first cache coherent subsystem verification solution for Arteris' Ncore interconnect. The Arteris Ncore interconnect is a configurable distributed heterogeneous cache coherent interconnect that enables SoC teams to efficiently design customised, fully coherent systems.

It has been announced today that the Software Integrity strategy from Synopsys has been expanded to address the cyber security and safety challenges faced by the automotive industry.

Synopsys has announced that it has completed the acquisition of Gold Standard Simulations (GSS), a leading provider of TCAD and EDA simulation solutions for design technology co-optimisation of advanced process nodes.

Synopsys has announced a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The solution provides a comprehensive process, transistor and circuit simulation flow that enables technology development and design teams to evaluate various transistor and process options using a design technology co-optimisation methodology that starts in the pre-wafer research phase.

Synopsys has revealed that the company's Custom Compiler tool has been enabled by Samsung for 14nm LPP and LPC FinFET production. The process delivers high performance for compute-intensive designs and lower power consumption for mobile applications.

Synopsys has completed its acquisition of Simpleware, a privately held, leading provider of software products for the conversion of 3D scan data into high-quality computer models used for engineering design and simulation.

Synopsys has revealed that Toshiba selected the company's IC Compiler II place and route solution as the plan-of-record across its groups for performance-critical designs including internal and external customer designs. Since its launch in 2014, IC Compiler II has rapidly established itself as the widely recognised solution of choice for high-performance designs.

Synopsys has announced the immediate availability of the 2016.03 release of its IC Compiler II place-and-route solution, further bolstering its leadership in Quality-of-Results (QoR) across a diverse application base. Excellent turnaround time coupled with achieved-QoR has led customers like HiSilicon and Movidius to select IC Compiler II as their primary implementation tool for their next-gen performance-critical designs.

Synopsys has announced the extension of its Safety Enhancement Package (SEP) to DesignWare ARC EM processors that include cache support and DSP acceleration. The ARC EM4, EM6, EM5D and EM7D cores, combined with the ARC SEP option, have been certified ASIL D Ready by SGS-TÜV Saar, a leading independent certification company.

Synopsys announces that key products in its functional safety verification solution are now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar, an independent accredited assessor, formally certified VCS Functional Verification solution, Certitude functional qualification solution and Verdi Debug solution with verification planning and coverage, following an industry-standard Functional Safety Tool Qualification.

Cadence Design Systems has announced that Tezzaron Semiconductor has adopted the Cadence full-flow digital Register-Transfer Level (RTL)-to-signoff solution for its networking and supercomputing SoCs, cutting its development schedules in half. Tezzaron has incorporated Cadence tools in its design work from the very beginning. Over the years, Tezzaron’s products have increased in size, sophistication and complexity, prompting the adoption of...

Synopsys has announced its next-gen VIP (Verification IP) for Micron's Hybrid Memory Cube (HMC) architecture. The HMC architecture offers a high performance, low cost memory solution, with 70% less energy utilisation than existing DRAM technologies. Synopsys VC VIP for HMC enables the design of next-generation high-speed memory technologies with ease of use, fast integration and optimum performance, resulting in accelerated verification closure.

Interoperable Process Design Kits (iPDKs) are now available from Dongbu HiTek and Synopsys that enable Dongbu HiTek foundry customers using Synopsys’ Custom Compiler solution to rapidly design specialised analogue/power and mixed signal chips that target high growth markets.