Gridbee Communications has achieved first-pass silicon success for its integrated IoT secure wireless communications solutions using Synopsys' silicon-proven DesignWare ARC EM6 Processor. Gridbee chose Synopsys' ARC EM processor over competitive processor alternatives for its superior power- and performance-efficiency, ability to secure code with advanced memory protection capabilities and availability of a comprehensive suite of tools and open s...

It has been announced that eWBM achieved first-pass silicon success for its MS1000 microcontroller with embedded security using Synopsys' DesignWare tRoot Secure Hardware Root of Trust, True Random Number Generator (TRNG), and Security Protocol Accelerator IP. The IP enables the implementation of a wide range of hardware-enforced security functions that help protect IoT devices against evolving threats and secure sensitive data such as encryption...

Synopsys has announced it will host the 8th annual CodenomiCON USA and showcase its Software Integrity Platform at Black Hat USA 2016. CodenomiCON is an exclusive cybersecurity thought leadership and networking event organised by Synopsys during Black Hat USA, one of the largest and most distinguished information security conferences in the world.

Aimed for use with Synopsys Virtualizer Development Kits (VDKs), a new model for Infineon’s latest TriCore architecture, TriCore 1.6.2, has been announced by Synosys.

Synopsys has announced the availability of the industry's first Verification IP (VIP) and UVM source code test suite for Ethernet 200G. As the requirements for increased bandwidth to support video-on-demand, social networking and cloud services continue to grow, Synopsys VC VIP for Ethernet 200G enables SoC teams to design next-gen networking products with better ease of use and higher verification productivity, resulting in accelerated verificat...

Synopsys has announced the version 3.8 release of its Seeker product, the company's innovative runtime security analysis solution and one of the latest additions to its Software Integrity Platform. Seeker analyses web application code and data flows at runtime using a technique known as an Interactive Application Security Testing (IAST), which detects and confirms exploitable security vulnerabilities and provides actionable guidance that enables ...

Synopsys has announced that the release of the PrimeTime static timing analysis tool includes a major enhancement to cut compute costs for timing closure by 10x. Through the use of smart Engineering Change Order (ECO) technology, this latest release reduces memory requirements by 5x and speeds runtime by 2x while maintaining industry-leading first-pass fix rate of 95%+.

Synopsys has revealed that TowerJazz has certified the company's IC Validator physical verification product for final signoff verification. Synopsys' ongoing programme to provide designers signoff solutions for the widest range of foundry technologies has grown to include TowerJazz's line of leading speciality processes.

The immediate availability of DesignWare MIPI CSI-2 Device Controller IP and DesignWare MIPI DSI Device Controller IP for mobile, automotive and IoT SoCs has been announced by Synopsys.

It has been announced by Synopsys that it has reduced the power and area of its DesignWare USB 2.0 Type-C Controller and PHY IP for cost-sensitive and energy-efficient IoT edge applications targeting 40 and 55nm ultra-low power processes. The IP cuts silicon area by up to 50% compared to competitive offerings, saving on average $0.03 per die. 

The next gen ATPG and diagnostics solution, TetraMAX II by Synopsys, incorporates the innovative test engines unveiled at the International Test Conference in October 2015. Delivering an order of magnitude faster runtime, TetraMAX II cuts ATPG runtime from days to hours, ensuring patterns are ready when early silicon samples are first available for testing.

It has been announced by Synopsys that its TetraMAX II Automatic Test Pattern Generation (ATPG) tool delivering 10 times faster run time and 25% fewer test patterns, is now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar GmbH, an independent accredited assessor, formally certified TetraMAX II, following an in-depth functional safety tool qualification. 

Synopsys has announced that STMicroelectronics is seeing significantly faster test pattern generation runtime and reduced number of patterns with TetraMAX II ATPG. STMicroelectronics faces the challenges of increasing complexity and shrinking time-to-market schedules for their SoC designs. 

Synopsys has announced that Toshiba has confirmed that Synopsys TetraMAX II ATPG can significantly accelerate test pattern generation and reduce manufacturing test time and cost. Required to meet aggressive test quality and design schedule goals on an upcoming complex SoC, Toshiba designers determined they would need a much faster ATPG solution that generates much fewer test patterns while being fully power-aware. 

Synopsys has announced the version 8.5 release of Coverity, the company's industry-leading static analysis tool and one of the core components of its Software Integrity Platform. Coverity is an automated software testing tool that analyses source code to detect critical security vulnerabilities and defects early in the software development lifecycle.

The HAPS adapter that enables a HAPS FPGA-based prototyping system to easily connect to a Juno ARM development platform has been annouced by Synopsys. This software development platform includes the Juno Versatile Express board with ARM Cortex-A72, or Cortex-A57 and Cortex-A53 MPCore, Mali-T624 and reference software through Linaro Linux.

Synopsys has announced a multi-year extension of its OEM agreement with Lattice Semiconductor for Synopsys' Synplify Pro FPGA synthesis tools. With this agreement, Synopsys continues to be the exclusive provider of logic synthesis technology optimised for the highest quality of results, area and runtime for designers targeting Lattice FPGAs and Complex Programmable Logic Devices (CPLDs).

An optimised version of the DesignWare PHY and Controller IP Solution for PCI Express (PCIe) 4.0 architecture has been released by Synopses, which reduces latency by up to 20% and area by 15% compared to the previous implementation.

Synopsys has announced the latest release of its RSoft Photonic System Design Suite, the company's software for the design of optical communication systems and Photonic ICs (PICs) at the signal propagation level. Version 2016.06 introduces a new interface to PhoeniX Software's OptoDesigner chip and mask layout tool to streamline design and fabrication processes for PICs.

Semiconductor Manufacturing International Corporation and Synopsys has announced immediate availability of their joint 28nm RTL-to-GDSII reference design flow. Developed through deep engineering collaboration between Synopsys and SMIC on the 28-nm High-K Metal Gate (HKMG) process technology, the flow is based on Synopsys' Galaxy Design Platform using key features from the IC Compiler II place and route solution, Design Compiler Graphical synthesi...