Search results for "Synopsys"
Synplicity’s Synplify Premier Platform Delivers Additional Time-to-Market Benefits and Expanded Device Support for FPGA Designers
Synplicity, Inc has announced that its Synplify Premier software has been enhanced to provide more time-to-market benefits to designers using high-density FPGAs. In release 9.0, the company’s award winning graph-based physical synthesis technology has been optimized for Xilinx Virtex-5 FPGAs to deliver exceptional timing closure, analysis and debug for these advanced devices. This latest release extends the graph-based physical synthesis techno...
Synplicity Announces Acquisition By Synopsys
Synplicity, Inc., a leading supplier of solutions for the design and verification of semiconductors, has signed a definitive agreement to be acquired by Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing. When completed, the acquisition will expand Synplicity’s product portfolio and extend the market reach of its industry leading products.
Synplicity Launches ReadyIP Program: the Industry’s first Universal, Secure IP Flow for FPGA Implementation
Synplicity®, Inc. today announced the ReadyIP Initiative, a program that takes aim at simplifying the access, evaluation, and use of intellectual property (IP) for FPGA-based system design. The ReadyIP program delivers the industry’s first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate and easily integrate IP from several third-party vendors within their designs using the Synplify Pr...
Synopsys And Synplicity Establish Alliance To Advance High-Performance ASIC Verification
Synopsys and Synplicity, have announced the signing of a joint marketing agreement intended to improve verification flows for their mutual customers. Under terms of the agreement, the companies intend to work together on next-generation, high-performance verification solutions for ASIC designers. Targeting FPGA-based prototyping environments, Synopsys and Synplicity plan to demonstrate Synopsys' VCS functional verification solution working se...
TI introduces first SuperSpeed USB-compliant transceiver test chip
Texas Instruments, an active member of the SuperSpeed USB 3.0 promoters group, has introduced a new 5-Gbps transceiver test chip designed to the USB 3.0 specification version 1.0. The new transceiver is capable of driving and receiving signals over 4-m USB 3.0 cables to ensure data integrity. This transceiver will be demonstrated at the USB Developers Conference in Tokyo, Japan on May 21-22.
New release of Lattice diamond design software delivers more robust design capabilities for low power, cost sensitive FPGA applications
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced release 1.3 of its Lattice Diamond® design software, the flagship design environment for Lattice FPGA products.
Cortus S.A. appoints Roddy Urquhart as Vice President Sales & Marketing
Cortus S.A., the technology leader in ultra low power, silicon efficient, 32-bit processor IP cores appoints Roddy Urquhart as Vice President Sales & Marketing with immediate effect. Dr Urquhart will focus on expanding the worldwide business of Cortus and on building its position in the market.
Sondrel wins Queen’s Award for Enterprise
Sondrel, the European physical implementation IC design house, has today been honoured with the Queen’s Award for Enterprise in the Innovation category. The award is the result of the company’s success – due in part to the flexible design methodology it has developed for managing costs and durations of projects, and a software environment that allows switching between third party tools for optimum results whilst incorporating debug and mana...
SynaptiCAD’s GOF fixes Logic Equivalence Check Failures - Whitepaper
SynaptiCAD’s Verilog netlist editor, Gates-on-the-Fly (GOF), has recently been updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. SynaptiCAD has also published a white paper that describes how the updated GOF was used to find and fix failures identified by Cadence’s Conforma...
VHDL/Verilog Converters upgraded for Verilog 2005
SynaptiCAD has upgraded the V2V tools that translate bidirectionally between Verilog and VHDL source code. These translators are primarily aimed at converting behavioral and/or RTL-level code and are most often used when a designer has received IP in another language than his preferred design language.