Search results for "Synopsys"
Synopsys and Arteris Enable Earlier Multicore SoC Architecture Optimization with Faster Turnaround Times
Synopsys, Inc. and Arteris Inc. today announced a collaboration that enables models of Arteris' FlexNoC interconnect IP to be used with Synopsys' Platform Architect environment, offering system designers the ability to simulate realistic system-level performance of their end product architectures.
Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
Synopsys, Inc. today announced immediate availability of DesignWare Embedded Memory and Logic Library IP for TSMC's 28-nanometer (nm) high-performance and high-performance for mobile process technologies. The Synopsys DesignWare Embedded Memories and Logic Libraries are designed to deliver high performance with low leakage and active power, giving engineers the ability to optimize their entire system-on-chip (SoC) design for speed and energy effi...
Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips
Synopsys, Inc. announced that its DesignWare STAR Memory System has shipped in one billion chips from semiconductor manufacturers worldwide, reinforcing its status as a trusted test and repair solution for embedded memories. The STAR Memory System is an advanced built-in-self-test solution that provides automated pre- and post-silicon memory test, debug and diagnostic capabilities. The automated BIST insertion and advanced repair features reduce ...
THERMINATOR Project Warms Efforts to Cool Semiconductor Design Solutions
The partners in a new EU-funded research project today announced details of the multinational/multidisciplinary program: “THERMINATOR — Modeling, Control and Management of Thermal Effects in Electronic Circuits of the Future”. This 3-year project is designed to maintain the strong positions that Europe’s semiconductor and electronics equipment companies have achieved in highly competitive application areas such as automotive systems and f...
STMicroelectronics Joins the IPL Alliance as the First Semiconductor Board Member
The Interoperable PDK Libraries (IPL) Alliance announced today that STMicroelectronics has joined the Alliance as the first semiconductor board member. STMicroelectronics brings years of experience in multi-vendor analog/mixed-signal design flows to further the IPL Alliance's efforts in creating and promoting interoperable process design kit (iPDK) standards.
International conference will tackle the impact of CMOS variability on the semiconductor industry
The National Microelectronics Institute (NMI), the trade association representing the semiconductor industry in the UK and Ireland, in collaboration with the UK’s nanoCMOS project, is to hold Europe’s first international conference dedicated to the subject of CMOS variability. The conference will take place on 23rd October at the Royal College of Physicians, London.
Lattice's new mixed signal design software simplifies platform management design
Lattice Semiconductor Corporation has announced release 6.1 of its PAC-Designer® mixed signal design software, with updated support for Lattice's Platform Manager™, Power Manager II and ispClock™ devices. Users designing with Platform Manager devices will now have access to the Lattice Diamond® 1.3 software design environment. This integration of the PAC-Designer 6.1 and Diamond 1.3 design software tools will make more advanced digital desi...
Vector Fabrics Joins The Synopsys System-Level Catalyst Program
Vector Fabrics announced today that it has joined Synopsys' System-Level Catalyst Program. Aimed at accelerating the adoption of system-level design, the program promotes interoperability between its partners' design solutions. The combination of system-level design tools from Synopsys and Vector Fabrics can increase the design productivity of systems engineers that develop multicore embedded systems.
Top EDA Companies Endorse Tensilica's Pin-Level SystemC Models
Tensilica has announced that it has expanded the range of processor modeling options with the introduction of pin-level SystemC models of its Xtensa customizable dataplane processors (DPUs). With this novel feature, Tensilica now offers the widest array of modeling choices of any provider of licensable microprocessor or DSP (digital signal processing) IP cores.
Zuken Launches Advanced Wire Harness Modeling and Simulation with Synopsys Saber
Zuken has introduced a new integration tool E³.Saber Frameway for Zuken’s cable design software E³.cable. This allows engineers to create right-first-time robust wire harness, hydraulic and pneumatic designs, helping them overcome growing harness complexity and time/quality constraints through early access to virtual prototyping results.