Search results for "Synopsys"
Lattice Announces New Release of IspLEVER Classic Design Tool Suite
Lattice Semiconductor Corporation today announced the immediate availability of its ispLEVER Classic version 1.5 design tool suite. This new Windows-based version is now available for download and licensing at no charge from the Lattice website, www.latticesemi.com/ispleverclassic. The comprehensive ispLEVER Classic 1.5 design software continues to support the ultra-low power ispMACH 4000ZE CPLD family as well as all of Lattice's mature programma...
New Release of Lattice Diamond Design Software Delivers More Rubust Design Capabilities for Low Power, Cost Sensitive FPGA Applications
Lattice Semiconductor Corporation has announced release 1.3 of its Lattice Diamond design software, the flagship design environment for Lattice FPGA products. Users of Lattice Diamond 1.3 software will benefit from major new features, including clock jitter analysis. Lattice Diamond 1.3 software is also now integrated with Lattice’s PAC-Designer 6.1 mixed signal design tools (also announced today), providing design support for Lattice’s pro...
Lattice announces new version of mixed signal design software
Lattice Semiconductor Corporation today announced release 6.2 of its PAC-Designer mixed signal design software, with updated support for Lattice’s Platform Manager, Power Manager II and ispClock devices. Users designing with Platform Manager devices now have more integrated access to the Lattice Diamond 1.4 software design environment, also announced today.
Synopsys NanoTime Enables Full Chip Transistor Level Timing Analysis on Cavium Networks OCTEON II Internet Application Processor
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today reported that Cavium Networks, Inc. used NanoTime transistor-level static timing analysis (STA) solution to achieve full-chip STA signoff for its next-generation internet application processor, OCTEON II that is shipping now.
Synopsys and Applied Materials Collaborate on TCAD Models for Next-Generation Logic and Memory Technologies
Synopsys, Inc. and Applied Materials, Inc. today announced a collaboration to develop technology computer-aided design (TCAD) models for next-generation semiconductor devices. The models derived from this TCAD collaboration will enable customers to speed up process development for 14-nanometer (nm) and 11-nm logic and new memory chip technologies, allowing them to lower cost and reduce time-to-market.
Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm Analog/Mixed-Signal Reference Flow 2.0
Synopsys announced that it has collaborated with TSMC to deliver Synopsys' custom design solution for TSMC's 28-nanometer (nm) Analog/Mixed-Signal (AMS) Reference Flow 2.0. Part of TSMC's comprehensive 28nm design infrastructure, the flow delivers new advanced automation capabilities to improve productivity and shorten the design cycle. The new capabilities include both parasitic-aware and Layout Dependent Effect (LDE)-aware design methodologies....
Synopsys Collaborates With STMicroelectronics to Help Achieve Critical Milestone in 20-nm Design
Synopsys announced its close cooperation with STMicroelectronics (ST) in the successful tapeout of ST's first 20-nanometer (nm) technology demonstrator test chip. This tapeout represents a critical milestone in the R&D collaboration between the two companies to develop a comprehensive design enablement solution for system-on-chip (SoC) integrated circuits (ICs) using ST's next-generation 20-nm process technology, co-developed with its ISDA (Inter...
Synopsys Announces Production-Ready Lynx Design System Optimized for Common Platform 28-nm High-K Metal Gate Technology
Synopsys announced it is delivering a low power, high-performance system-on-chip (SoC) design solution optimized for the Common Platform alliance (CPA) 28-nanometer(nm) high-k metal gate (HKMG) technology. Based on Synopsys' Lynx Design System and its Galaxy™ Implementation Platform-enabled flow with Synopsys DesignWare Interface IP, this solution was built through a multi-year collaboration with ARM and the Common Platform alliance [IBM, Samsu...
Synopsys TetraMAX ATPG cuts test development schedule at Arrow Electronics
Synopsys has announced that Arrow Electronics successfully deployed Synopsys’ TetraMAX automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high quality manufacturing tests. Stringent quality goals combined with increasing design complexity stimulated the need to improve ATPG performance at Arrow. By utilising TetraMAX ATPG’s multicore processing capability on their quad-core ...
Synopsys delivers HDMI IP solution for 90nm to 40nm process technologies
Synopsys has announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys’ DesignWare IP portfolio. Synopsys’ DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability a...