Search results for "EDA"
Cadence and Xilinx Introduce FPGA IP Ecosystem Microsite
Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, and Xilinx today introduced the new Xilinx IP Ecosystem microsite, a unified site meant to increase FPGA and ASIC designers’ visibility to the latest IP supporting the Xilinx programmable platform.. The microsite, developed as part of a broad initiative announced by Xilinx to transform and enable its ecosystem of third-party providers, is part of the C...
Cadence Completes Acquisition of Denali
Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronics design innovation, today announced that it has successfully completed the acquisition of Denali Software, Inc., a Sunnyvale, Calif.-based provider of electronic design automation (EDA) software and intellectual property (IP).
Aptina Picks Silicon Frontline’s Post-Layout Verification EDA Software to Eliminate Costly Prototype Builds, Improve Manufacturing Quality
Silicon Frontline Technology, an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that Aptina, the world's foremost image sensor provider, is using Silicon Frontline’s F3D (Fast 3D) software for post-layout verification and for fast 3D extraction to improve Aptina’s image sensor design accuracy and manufacturing quality.
Magma’s Titan and FineSim Validated for LFoundry Interoperable Process Design Kits Accelerating Turnaround Time for Analog/Mixed-Signal SoCs
Magma Design Automation today announced the LFoundry’s interoperable process design kits are validated for use with the Titan Mixed-Signal Design Platform, Titan Acclerators and FineSim circuit simulator for 0.15-micron technology platforms. The combination of Magma’s Titan and FineSim software and LFoundry’s process technology will accelerate development of analog/mixed-signal (AMS) products, especially for European system-on-chip (SoC) de...
ARM Physical IP Production Characterization System Utilizes Magma SiliconSmart Software
Magma Design Automation announced today that ARM (LSE: ARM; Nasdaq: ARMHY) has successfully utilized Magma’s SiliconSmart characterization and modeling software suite to enhance and expand ARM’s production characterization system for Physical IP products. This fast, accurate and easy-to-use characterization system will assist ARM in delivering standard cell and I/O libraries.
TSMC Qualifies Magma's QCP Extractor for 28-nm Designs
Magma Design Automation Inc., a provider of chip design solutions, today announced TSMC has included the QCP™ extractor in TSMC’s quarterly EDA qualification report for 28-nanometer (nm) integrated circuits (ICs). This qualification gives designers additional confidence in using QCP to address the increasing complexity of ICs implemented in TSMC’s 28-nm processes.
Magma’s Quartz DRC Physical Verification Solution Qualified to Support GLOBALFOUNDRIES’ DRC+ Flow for Technologies at 28 nm and Below
Magma® Design Automation have announced that the new pattern matching capability in the Quartz™ DRC physical verification product has been qualified to support DRC+, GLOBALFOUNDRIES' silicon-validated, yield-critical pattern-based design for manufacturing (DFM) verification flow for all advanced process technologies, including 40 nanometer (nm), 28 nm and below.
Fujitsu Semiconductor Standardizes on Mentor Graphics HyperLynx Signal Integrity Technology as LSI-PKG-PCB Co-Design Tool
Mentor Graphics Corporation has announced that Fujitsu Semiconductor has standardized on the Mentor Graphics HyperLynx Signal Integrity technology as the company’s LSI-IC Packaging (PKG)-Printed Circuit Board (PCB) co-design tool for fast and accurate high-speed simulation and analysis. For today's highly functional end-products, bus speeds are increasingly getting faster and the demand for noise timing-aware LSI-PKG-PCB co-design is increasing...
New Generation EDA Software improves Testbench Quality for BSDL Verification
At the 2010 International Test Conference (ITC), GOEPEL electronic, a global leader in JTAG/Boundary Scan solutions, introduces TAP Checker™ a new generation EDA software tool for verification of BSDL (Boundary Scan Description Language) files and validation of JTAG implementations in integrated circuits. The innovative tool suite enables the automatic generation of simulation vectors and test patterns for chip-level validation and verification...
Teklatech will make Worldwide Debut at DATE Exhibition in March
Start-up EDA company, Teklatech will debut its new EDA software tool, FloorDirector, at the DATE show March 10-14 ICM in Munich. Using its new floorplanning and clock distribution technology, semiconductor vendors can overcome critical dynamic voltage drops which can result in unpredictable signal integrity and noise effects that can cause silicon failure.