Search results for "EDA"

Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence® Silicon Realization product line. Open-Silicon completed the entire design using Cadenc...

Cadence today announced significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

Cadence Design Systems today announced that the company will be presenting a paper and showcasing its technology at RTI's 3D Architectures for Semiconductor Integration and Packaging conference. The conference will be Dec. 8 to 10 at the Hyatt Regency San Francisco Airport Hotel in Burlingame.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Fujitsu Limited has adopted the Cadence® Encounter® Conformal® ECO Designer to cut costs and reduce design time in its engineering change order (ECO) implementation flow. The technology giant recently deployed the Cadence technology to tape out a network-control large-scale integration design of 40 million gates at a 65-nanometer ...

Cadence introduced the Cadence SOI Design Hub, a new Web portal that lowers the barriers to adopting silicon-on-insulator (SOI) technology through comprehensive silicon-proven design enablement solutions and services. The SOI Design Hub is aimed at reducing SOI adoption start-up costs, cutting time to market for SOI intellectual property (IP), and improving design quality.

Cadence announced the immediate availability of verification IP (VIP) for ARM Ltd.’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices.

Xilinx and Cadence Design Systems have announced that they have teamed to develop the industry’s first virtual platform to enable system design, software development, and testing of Xilinx Zynq-7000 Extensible Processing Platform based systems in advance of hardware availability. This solution further enhances the development environment being put into place for Xilinx’s ARM processor-based processing platform and changes the development flow...

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, and Xilinx today introduced the new Xilinx IP Ecosystem microsite, a unified site meant to increase FPGA and ASIC designers’ visibility to the latest IP supporting the Xilinx programmable platform.. The microsite, developed as part of a broad initiative announced by Xilinx to transform and enable its ecosystem of third-party providers, is part of the C...

Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronics design innovation, today announced that it has successfully completed the acquisition of Denali Software, Inc., a Sunnyvale, Calif.-based provider of electronic design automation (EDA) software and intellectual property (IP).

Silicon Frontline Technology, an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that Aptina, the world's foremost image sensor provider, is using Silicon Frontline’s F3D (Fast 3D) software for post-layout verification and for fast 3D extraction to improve Aptina’s image sensor design accuracy and manufacturing quality.