Search results for "EDA"
Maia EDA launches new automated verification tool
Maia EDA has today announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initia...
X-FAB Qualifies Cadence Physical Verification System for All Process Nodes
Cadence Design Systems announced that X-FAB has qualified the Cadence Physical Verification System (PVS) for the majority of its process technologies. Foundry qualification means that X-FAB has given its stamp of approval for silicon accuracy of the Cadence Physical Verification System across all of its process nodes, and that mixed-signal customers can reap new performance and productivity advantages enabled by its tight integration into the Cad...
Cadence Strengthens Virtuoso Custom IC Design Leadership
Cadence Design Systems today extended its leadership position in analog and mixed-signal chip design technologies with the introduction of dramatic improvements to its leading Virtuoso IC design platform. Cadence announced powerful performance, capacity and usability enhancements in Virtuoso IC6.1.4 that reduce overall design time while ensuring high-quality production ICs.
Open-Silicon Achieves Ultra High Performance Using Cadence Silicon Realization Technology to Tape-Out Breakthrough 2.4 GHz ASIC Processor
Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence® Silicon Realization product line. Open-Silicon completed the entire design using Cadenc...
Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design
Cadence today announced significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.
Cadence to Present and Showcase Technology at RTI's 3D Architectures for Semiconductor Integration and Packaging Conference
Cadence Design Systems today announced that the company will be presenting a paper and showcasing its technology at RTI's 3D Architectures for Semiconductor Integration and Packaging conference. The conference will be Dec. 8 to 10 at the Hyatt Regency San Francisco Airport Hotel in Burlingame.
Fujitsu Adopts Cadence Encounter Conformal ECO Designer
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Fujitsu Limited has adopted the Cadence® Encounter® Conformal® ECO Designer to cut costs and reduce design time in its engineering change order (ECO) implementation flow. The technology giant recently deployed the Cadence technology to tape out a network-control large-scale integration design of 40 million gates at a 65-nanometer ...
Cadence Announces Comprehensive SOI Design Hub
Cadence introduced the Cadence SOI Design Hub, a new Web portal that lowers the barriers to adopting silicon-on-insulator (SOI) technology through comprehensive silicon-proven design enablement solutions and services. The SOI Design Hub is aimed at reducing SOI adoption start-up costs, cutting time to market for SOI intellectual property (IP), and improving design quality.
Cadence Accelerates Development of Multiprocessor Mobile Devices with New ARM ACE Verification IP
Cadence announced the immediate availability of verification IP (VIP) for ARM Ltd.’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices.
Xilinx and Cadence Introduce an Extensible Virtual Platform to Enable Software-Centric Approach for Embedded Software Developers
Xilinx and Cadence Design Systems have announced that they have teamed to develop the industry’s first virtual platform to enable system design, software development, and testing of Xilinx Zynq-7000 Extensible Processing Platform based systems in advance of hardware availability. This solution further enhances the development environment being put into place for Xilinx’s ARM processor-based processing platform and changes the development flow...