Search results for "EDA"

Synopsys has announced that Hisilicon Technologies Co., Ltd., a worldwide provider of ASICs and solutions for communication network and digital media, and a subsidiary of Huawei Technologies, has established Synopsys as its primary EDA partner across its implementation and verification design flows. Hisilicon has signed an expanded business agreement to extend its use of Synopsys' IC Compiler place-and-route technology and DesignWare(R) IP as wel...

Synopsys, Inc. announced that Accellera Systems Initiative will receive Synopsys' twelfth annual Tenzing Norgay Interoperability Achievement Award for advancing industry standards that enable interoperable system design flows. The Accellera Systems Initiative was formed in December 2011 through the merger of Open SystemC Initiative and Accellera.

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that TSMC has successfully taped out a complex 28-nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys' Galaxy™ Implementation Platform. Key features used to design the PQV test chip include 28-nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (U...

Synopsys has signed a definitive agreement to acquire Magma Design Automation Inc. a provider of chip design software headquartered in San Jose, California. Bringing together complementary technology, development and support capabilities will enable the combined company to more rapidly meet customer requirements linked to chip designs at both leading-edge and mature process nodes.

Synopsys, Inc. will host several special events at the Design Automation Conference, June 3 - 7 in San Francisco, California. The events will feature speakers from leading semiconductor companies, IP providers, foundries and Synopsys.

To address increasing customer demand for integrated layout and 3D full wave analysis, CST and Cadence are collaborating to provide a best in class solution. A webcast on June 23 will demonstrate the integration.

Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, in collaboration with imec’s 3D integration IIAP (industrial affiliation program), have jointly developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. Imec and Atrenta will be demonstrating this flow at the Design Automation Conference (DAC) in San Diego, CA from June 6 – 8, 2011.

Maia EDA has today announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initia...

Cadence Design Systems announced that X-FAB has qualified the Cadence Physical Verification System (PVS) for the majority of its process technologies. Foundry qualification means that X-FAB has given its stamp of approval for silicon accuracy of the Cadence Physical Verification System across all of its process nodes, and that mixed-signal customers can reap new performance and productivity advantages enabled by its tight integration into the Cad...

Cadence Design Systems today extended its leadership position in analog and mixed-signal chip design technologies with the introduction of dramatic improvements to its leading Virtuoso IC design platform. Cadence announced powerful performance, capacity and usability enhancements in Virtuoso IC6.1.4 that reduce overall design time while ensuring high-quality production ICs.