Search results for "Synopsys"
Collaboration to accelerate adoption of 28nm FD-SOI technology
Synopsys has announced it has extended its collaboration with STMicroelectronics to include Samsung Electronics, enabling broader market adoption of ST's 28-nm FD-SOI technology for SoC design. Synopsys' Galaxy Design Platform is production-proven on multiple designs based on ST's 28-nm FD-SOI technology.
Collaboration results in 14nm tri-gate design platform
A broad SoC design enablement for Intel's 14nm Tri-Gate process technology, for use by customers of Intel Custom Foundry, has been announced in a joint statement by Synopsys and Intel. The Intel Custom Foundry 14nm design platform supports Synopsys' industry-leading Galaxy Design Platform tools and RTL to GDSII methodology, high performance DesignWare Memory Compiler IP, and advanced interface IP.
Processors optimised for low-power embedded DSP applications
Designed for low-power embedded digital signal processing applications, the DesignWare ARC EM DSP family of processors has been introduced by Synopsys. The processors are implementations of the ARCv2DSP instruction set architecture (ISA), an enhancement to the efficiency-optimised ARCv2 ISA with over 100 new DSP instructions for accelerating signal processing algorithms, including vector and complex MUL/MAC operations.
Complete PCI Express 4.0 IP solution targets enterprise computing
A completePCI Express 4.0 IP solution, which Synopsys claims as an industry first, is now available to designers. Consistingof DesignWare PHY, controllers and verification IP, the solution targetsenterprise computing applications such as servers, networking, storage systems and SSDs.The PCI Express 4.0 specification doubles throughput to 16 GT/s and is currently at a preliminary revision 0.3 within the PCI Special Interest Group (PCI-SIG).
DesignWare IP validated in the TSMC 16nm FinFET process
The validation ofDesignWare IP in the TSMC 16-nm FinFET process technology has been announced by Synopsys. Designers developing SoCs in TSMC's 16-nm FinFET process can take advantage of the doubled transistor density, which reduces power consumption by up to 55% or increases performance by up to 35% compared to TSMC's 28-nm process.
Invionics Unveils VRDM Development Platform for Rapid Deployment of Verific HDL Parsers
Invionics took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.
Decoder supports multiple DTS audio formats
Providingmanufacturerswith a single technology solution for decoding all DTS 5.1 channel audio formats, Synopsys have made availablethe DTS-HD audio decoder optimised for its DesignWare ARC AS211SFX and AS221BD Audio Processors.
IC design consultancy to present at conference
Sondrel is to share its expertise at the forthcoming NMI conference "Accelerating Verification - faster, smarter?".Wayne Wu, Sonderl's Business Development Director of its Verification Services, will be giving the presentation at the conference, attended by members of the UK electronic systems, microelectronics and semiconductor industry.
Design for test tool shrinks manufacturing costs
Synopsys says that Dialog Semiconductor has successfully deployed Synopsys' DFTMAX Ultra product on a mixed-signal test chip to lower manufacturing test costs. Built into Synopsys' Design Compiler RTL synthesis and linked to Synopsys' TetraMAX ATPG, DFTMAX Ultra was deployed on the design in a single day and delivered 3X higher time compression.
Software deployment results in 10% higher performance
A supplier ofend-to-end interconnect solutions for data center servers and storage systems,Mellanox Technologies,has standardized on Synopsys' Design CompilerGraphical RTL Synthesis solution for the design of their interconnect products. The deployment ofDesign Compiler Graphical has resulted in a Mellanox realising a10% higher performance, lower area and a highly convergent design flow.