Search results for "Synopsys"
Controller and PHY IP utilised by 00m+ production SoCs
DesignWare USB 3.0 Controller and PHY IP, manufactured by Synopsys, has shipped more than 100m production SoCs used in mobile computing, digital home and cloud computing applications. The DesignWare USB 3.0 Controller and PHY IP has been integrated into the SoCs of products from more than 60 companies, including Microsoft's XBOX One.
Emulex has adopted Synopsys' VIP for the Ethernet protocol
Synopsys has announced that Emulexhas adopted it's Verification IP (VIP) for the Ethernet 1G/10G/40G/100G protocol. This is based onSynopsys' SystemVerilog and UVM architecture, offering ease of use, ease of integration, performance, configurability, coverage, and debug within UVM environments. The VIP also supportsSynopsys' Protocol Analyzer, a protocol-centric debug environment.
NVM IP is 75% smaller than alternatives & reduces test times by 3X
Claiming to be up to 75% smaller than alternative NVM IP solutions, the DesignWare AEON Trim NVM IP for high-voltage processes has been launched by Synopsys. Faster programming times reduce NVM test times by 3X compared to alternative NVM solutions, enabling designers to reduce production test times and minimize test costs for automotive and industrial ICs.
Synopsys Announces Immediate Availability of Broad Portfolio of IP for TSMC 28HPC Process
Synopsys, Inc announced the immediate availability of a wide range of DesignWare interface, analog, logic library and embedded memory IP for TSMC's 28-nanometer (nm) high-performance compact (HPC) process. Synopsys' production-ready DesignWare IP reduces risks for designers who want to take advantage of the lower power consumption, area reduction and performance improvements that the TSMC 28HPC process offers. The DesignWare IP portfolio for the ...
Synopsys Redefines the IP Supplier Paradigm with New IP Accelerated Initiative
Synopsys, Inc announced the IP Accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their system-on-chips (SoCs). This initiative augments Synopsys' established broad portfolio of silicon-proven DesignWare IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With ...
Samsung and Synopsys Deliver Design Tools and IP for 14-nm FinFET Process
Synopsys, Inc announced certification and immediate availability of a comprehensive design solution and semiconductor intellectual property (IP) for Samsung's 14-nm FinFET process.
Synopsys Announces HAPS Connect Program to Speed Creation of HAPS FPGA-Based Prototypes
Synopsys, Inc announced the launch of its HAPS Connect Program to broaden hardware and service offerings for Synopsys HAPS prototyping systems. Back9 Design, eInfochips, Fidus, Gigafirm, hd Lab and Sarokal are the first companies to sign multi-year agreements to provide daughter boards, mechanical design services and protocol testing for Synopsys HAPS systems.
Collaboration targets NBTI degradation at 14nm node & beyond
In a bid to advance the modeling of negative bias temperature instability (NBTI), Synopsys have announced a collaboration with the Indian Institute of Technology. The collaboration aims to provide semiconductor manufacturers with an insight into NBTI degradation and develop methods to mitigate its effects on FinFETs at the 14nm node and beyond.
Next-Gen Static & Formal Technology for Verification Compiler
Synopsys has announced the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.
DDR and LPDDR Verification IP Now Broadly Available
Synopsys has announced the release of its DDR4/3 and LPDDR4/3/2 Verification IP (VIP) available as part of Synopsys' Verification Compiler solution and as standalone titles. Based on 100 percent native SystemVerilog, the memory VIP includes built-in support for RDIMM and LRDIMM models, Verdi Protocol Analyzer debug capability and integrated verification plans, all designed to enable users to accelerate the verification of memory interfaces and ac...