Search results for "Synopsys"

Moving to a virtual development environment for automotive control embedded software. By Marc Serughetti, Synopsys.

The DesignWare HDMI 2.0 TX and RX controller and PHY IP, developed by Synopsys, have been certified by an HDMI authorised testing centre. The company’s HDMI 2.0 IP with Elliptic Technologies' HDCP embedded security module also achieved HDCP 2.2 certification, enabling the highest content protection over the HDMI 2.0 interface for HD multimedia SoCs.

Synopsys has expanded its memory Verification IP portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI UniProand JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and SoC designs.

Synopsys has announced that Fuzhou Rockchip achieved first-pass silicon success for its mobile application processor SoC using a wide range of Synopsys' DesignWareIP. Rockchip reduced time-to-market by months and made a head start over their competition in the fast-moving mobile industry by integrating DesignWare PHY and Controller IP for a range ofUSB,HDMIandMIPIIP.

Enabling over 50 successful tapeouts in the nine months since it became generally available, Synopsys' PrimeTime ADV advanced timing closure and signoff solution has been adopted by more than 70 leading semiconductor companies. According to Synopsys, the key to its adoption is ease of integration into existing timing closure flows, fast turnaround time and the ability to reduce timing Engineering Change Order (ECO) iterations on designs.

Synopsys has announced the expansion of its collaboration with imec into the fields of nanowire and other devices such as FinFETs and Tunnel-FETs, targeting the 5nm technology node and beyond. The agreement enables Synopsys to deliver accurate, process-calibrated models for its Sentaurus Technology Computer Aided Design (TCAD) tools to semiconductor manufacturers for use during 5nm technology node research and development.

Synopsys has revealed that more than 100 debug and analysis apps have been developed through the VC Apps open interfaces. Offering access to additional debug and analysis capabilities for all Verdi users, the apps are available through the Verdi VC Apps ToolBox and the VC Apps Exchange website.

Designed to simplify the design process of aerospace applications, the ATMX150RHA mixed-signal ASIC platform has been released by Atmel. Manufactured on 150nm Silicon on Insulator, the platform expands the company’s portfolio of radiation-hardened (rad-hard) solutions.Delivering up to 22m routable gates, the ASIC platform features non-volatile memory blocks and a flexible form factor with compiled SRAM and DPRAM blocks.

Synopsys' Coverity Scan Project Spotlight report, which analysed the defects in big data projects detected by the Coverity Scan open source software scanning service, found that the average defect density rate for the projects decreased since the release of the 2013 Coverity Scan Report. In a sample of 16 big data projects that included Apache Hadoop, HBase and Cassandra, the data showed Synopsys' Coverity business group attributed the defect den...

Synopsys has announced VIP (Verification IP) for LPDDR4, based on a 100% native SystemVerilog Universal Verification Methodology (UVM) architecture to enable ease of use, ease of integration and performance. Complete with verification plans, built-in coverage and a protocol-aware memory debug environment, Verdi Protocol Analyzer, Synopsys VIP for LPDDR4 is a complete VIP solution that accelerates verification closure for designers of low power me...