Search results for "Synopsys"

Following its acquisition of EDA Playground earlier this year, Doulos has announced its extended support for its growing community of users worldwide with the addition of the Synopsys VCS Functional Verification Solution. Doulos plans include innovations and extensions to EDA Playground in support of the roll-out of online training and blended learning solutions.

Computer Simulation Technology has demonstrated an innovative workflow that combines the full wave simulation and extraction capabilities of CST STUDIO SUITE with the accuracy of Synopsys HSPICE at booth #2827 during DAC 2015. Engineers concerned with the design of modern electronic systems can take advantage of this newworkflow.

Synopsys has announced that Broadcom has extended its license agreement, providing access to Synopsys' DesignWare ARC processors for an expanded range of advanced multimedia and networking SoC designs. Broadcom has standardised on Synopsys ARC processors to deliver advanced video compression capabilities in its SoCs for high-volume consumer devices.

Synopsys has announced the availability of Verification IP (VIP) for the DDR4 3D Stacking (3DS) specification. Synopsys VIP for DDR4 3DS, based on its native SystemVerilog UVM architecture, is architected for ease of integration and configurability. The VIP for DDR4 3DS supports all JEDEC commands and provides pre-built DIMM (UDIMM, RDIMM, LRDIMM) models with protocol and timing checks, including support for memory vendor and the JEDEC standard p...

CEA-Leti hasannounced that seven partners have joined its FD-SOI IC development programme, Silicon Impulse, launched to provide a comprehensive IC technology platform that offers IC design, advanced intellectual property, emulator and test services along with industrial Multi-Project Wafer (MPW) shuttles.

Synopsys has expanded its IP Accelerated initiative with support for ARM processors with the DesignWare Hybrid IP prototyping kits. The kits enable designers to prototype the ARM processor and memory elements of a design in a virtual environment for superior debug visibility, and to develop software for the DesignWare interface IP in an FPGA-based environment for high-performance execution with real-world interface connectivity.

Synopsys has announced it has signed a definitive agreement to acquire Codenomicon. The additional talent, technology and products will expand Synopsys' presence in the software security market segment and extend the Coverity quality and security platform to help software developers throughout various organisations quickly find and fix security vulnerabilities and protect applications from security attacks.

Synopsys has released extensions to its open-source Interconnect Technology Format (ITF) which enable modelling of complex device and interconnect parasitic effects at the advanced 10nm process node. The extensions include modelling of variation effects due to Multi-Patterning Technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB), an IEEE-ISTO Federation Member Program, to define an...

To enable designers to integrate required functionality in mobile and enterprise SoCs with less risk, Synopsys has introduced a portfolio of DesignWare PHY IP for TSMC's 16nm FinFET Plus (16FF+) processes. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCIe 4.0, 3.0 and 2.0; SATA ...

Synopsys has announced that TSMC has concluded 16nm FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys' custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys' Galaxy Design Platform for 16nm production designs and 10nm early engagements.