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Enabling designers to starttheir MAX 10 FPGA designs immediately, Altera have announcedthe availability of Quartus II beta software and early access documentation for MAX 10 FPGAs.Based on TSMC’s 55nm embedded flash process technology, MAX 10 FPGAs revolutionize non-volatile FPGA integration by delivering advanced processing capabilities into a small form factor, low-cost, instant-on programmable logic device.

Synopsys has announced availability of the V1.0 certified solution for cell-based and custom implementation with the TSMC N16 FinFET process. The TSMC-certified solution delivers predictable design closure with production-ready FinFET design automation tools, allowing engineers designing next generation semiconductors to deliver faster, more power-efficient and denser chips.

Uniquify has claimed to have achieved the industry’s fastest DDR4 performance in silicon of 2800Mb/s. The combination of Uniquify’s adaptive DDR4 intellectual property (IP) and SK Hynix’s high-performance DDR4 SDRAM memory components is operating at 2800Mb/s in a system implemented using TSMC’s 28HPM process technology.

Altera’s 20nm Arria 10 FPGAs and SoCs are now available in TSMC’s patented, fine-pitch copper bump-based packaging technology. Altera is the first company to adopt this technology in commercial production. “TSMC has provided a very advanced and robust integrated package solution for our Arria 10 devices, the highest-density monolithic 20 nm FPGA die in the industry,” said Bill Mazotti, vice president of worldwide operation...

Digital tools fromCadence Design Systems have received V1.0 DRM and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence tools.Cadence’s digital, custom/analog and signoff tools have been co-optimized with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.

Mentor Graphics has announced that itsIC design to silicon solution has achieved certification for TSMC’s Design Rule Manual (DRM) and SPICE model version 1.0 for its 16nm FinFET process.The certification includes tools in the Calibre physical verification and DFM platform, as well as the Olympus-SoC place and route system, the Pyxis custom IC design platform, and Eldo SPICE simulator.

Dolphin Integration announce the launch of sCODp-MT1-VD.02, a voice-oriented converter supporting both analog and digital microphones. It offers high dynamic range over gain range on ADC of 105dB and motor and wind noise filters to reduce the environment disturbance and enhance the voice recognition quality.

JVD announce the availability of a second critical piece of IP for Analog Front Ends. Following the announcement of the SCi310 Current to Voltage Converter in January, JVD, in conjunction with Systemcom, has made available two additional IP blocks designed for conditioning signals from sensors where the generic information about the phenomenon being detected, whether light or other physical or chemical or electromechanical apparatus, passes the f...

IC Insights has released their 2013 ranking of semiconductor companies by R&D spending. Intel continued to top the list, accounting for 37% of the top-10 spending and 19% of total worldwide semiconductor R&D expenditures. Intel’s R&D spending was more than triple that of second-place Qualcomm.

Designed as a silicon IP module to be integrated with additional circuitry unique to the customer’s application needs, the SCi310critical Analog Front End IP block has been intoduced by JVD. It is suitable for conditioning signals from sensors where the generic information about the phenomenon being detected, whether light or other physical or chemical or electromechanical apparatus, passes the first electrical conversion as a current.