Search results for "TSMC"

Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing with noise issues in a mixed-signal SoC embedding multiple power domains with diverse power modes.

Cadence Design Systems announced that it has received four TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform (OIP) Ecosystem Forum. Cadence was presented with awards for the joint delivery of the 7nm mobile design platform, the 7nm HPC design platform, the Integrated Fan-Out (InFO) design solution and its analog/mixed-signal IP.

The successful tapeout of multiple customer test chips with DesignWare Logic Libraries and Embedded Memories for TSMC's 7nm FinFET process has been announced by Synopsys. The tapeouts mark a significant milestone in Synopsys' and TSMC's collaboration on the development of DesignWare Logic Library, Embedded Memory and Interface IP for TSMC's 7nm FinFET process.

Synopsys announced that TSMC has certified the complete suite of Synopsys' digital, signoff and custom implementation tools for TSMC's most advanced 7 nm FinFET technology node. With multiple designs already under development by early adopters of 7nm technology, this certification enables mutual customers to derive the maximum benefits of the new technology node using IC Compiler II.

Synopsys announced that TSMC is recognising Synopsys with three "2016 Partner of the Year" awards for Interface IP and joint development of 7-nm mobile and HPC design platforms. Synopsys and TSMC have been collaborating for more than 16 years, most recently to accelerate the adoption of FinFET technology for optimum power, performance and area for the 7-nm process.

For RFID Tags, dynamic power is a critical factor as the capability for lower power translates immediately into a wider range of detection (RFID tag read range) and/or a highest identification rate in the same range. The main degree of freedom to improve power and area of RFID tag is located in the digital block. The SESAME eLC standard cell library enables up to 50% savings of dynamic power when compared to any other logic library available at 1...

Renesas Electronics and TSMC have announced that they are collaborating on 28nm eFlash process technology for manufacturing MCUs targeted at next-gen green and autonomous vehicles. The automotive MCUs employing this new 28nm process technology are slated for sample shipment and mass production in 2017 and 2020, respectively.

Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. As a result of the joint work, Cadence digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal po...

Synopsys announced its collaboration with TSMC to deliver innovative technologies to enable adoption of TSMC's High Performance Compute (HPC) Platform. The new technologies, enabled through TSMC and Synopsys collaboration, will be available in the Synopsys' Galaxy Design Platform for the 7 nm process in November 2016.

Cadence Design Systems has announced a broad portfolio of Cadence interface and Denali memory IP solutions for automotive applications supporting TSMC’s 16nm FinFET Compact (16FFC) process. By offering a wide array of IP using TSMC’s 16FFC process, Cadence is enabling automotive customers to accelerate time to market while gaining the benefits of TSMC’s most advanced process technology used in automotive applications.