Search results for "EDA"

Aldec has launched HES-DVM Proto Cloud Edition (CE). Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and has a focus on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.

Cadence Design Systems has announced that JVCKENWOOD has adopted the new Spectre FX Simulator and multiple Cadence custom, analogue, digital and verification solutions to accelerate IC development of its consumer electronics applications while minimising overall design risk.

Jeroen Leinders, Global eCADSTAR Solutions Leader and Chris Hambleton, General Manager, Zuken, address the pain points in schematic and PCB design.

Tiempo Secure and IC’Alps have announced a strategic collaboration to widespread silicon implementation of Common Criteria (CC) EAL5+ grade Secure Element cores for IoT applications. Specifically, Tiempo Secure is relying on IC’Alps’ expertise in physical design implementation to develop the hard macro of its Secure Element named TESIC, from netlist to GDSII.

Imperas Software has made available the first release of riscvOVPsimCOREV as free ISS (Instruction Set Simulator) based on the Imperas reference models of the OpenHW Groups processor RISC-V core IP.

The end of Moore’s law has been signaled for some time, but without a doubling of the number of transistors, battery-powered mobile devices rely on it to increase computing complexity. Gordon Allan offers a survival guide to life outside Moore’s law

Aldec has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs).

Digi-Key Electronics is collaborating with SnapEDA, to provide over 1.5 million verified and high-quality symbols, footprints, and 3D models for Digi-Key parts.

Synopsys and Samsung Foundry has announcedthe release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving and advanced driver-assistance systems (ADAS) applications.

Deca has announced the signing of an agreement with ADTEC Engineering to join its new AP Live Network. The partnership allows ADTEC to embed an AP Connect module into its new 2µm Laser Direct Imaging (LDI) system to natively process unique Adaptive Patterning (AP) designs in real-time.