Search results for "EDA"

Synopsys has announced that Shankar Krishnamoorthy has been promoted to GM of the Digital Design Group. Krishnamoorthy, who rejoined Synopsys in 2017, is an electronic design automation veteran with 25 years of experience bringing to market high-value, market-leading physical design and logic synthesis solutions.

Mentor has announced that Calibre nmPlatform and Analog FastSPICE (AFS) custom and analogue/mixed-signal (AMS) circuit verification platform are now qualified for Samsung Foundry’s newest process technologies. Customers can now use these offerings on Samsung’s 5/4-nanometer FinFET processes for the verification and sign-off of production tapeouts for their most advanced IC designs.

Modern design techniques have evolved substantially to allow for today’s engineer to focus on their unique value add, rather than need to reinvent the wheel for every new invention. And yet it’s widely accepted that nearly 75% of Internet of Things (IoT) projects fail. By Robbie Paul, Director, IoT business development for Digi-Key Electronics

Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.

Siemens has announced the expansion of its ODB++ language intelligent, single data-structure for transferring PCB designs into fabrication, assembly and test with a unified electronics manufacturing solution of open data formats for the entire digital thread.

Ten new Verification IP (VIP) solutions that allow engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols have been released by Cadence Design Systems.

Arm Flexible Access for Startups is an extension of its already highly successful Flexible Access program.

AMD has announced that it is extending the 2ndGen AMD EPYC processor family with three new processors that combine the balanced and efficient AMD Infinity architecture with higher speed 'Zen 2' cores for optimal performance on database, commercial High Performance Computing (HPC) and hyperconverged infrastructure workloads.

Aldec has enhanced its unified requirements lifecycle management EDA tool, Spec-TRACER, to support the exchange of system and hardware data with IBM Requirements Engineering DOORS Next product, commonly used by system engineers.

Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).