Search results for "EDA"

Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.

Siemens has announced the expansion of its ODB++ language intelligent, single data-structure for transferring PCB designs into fabrication, assembly and test with a unified electronics manufacturing solution of open data formats for the entire digital thread.

Ten new Verification IP (VIP) solutions that allow engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols have been released by Cadence Design Systems.

Arm Flexible Access for Startups is an extension of its already highly successful Flexible Access program.

AMD has announced that it is extending the 2ndGen AMD EPYC processor family with three new processors that combine the balanced and efficient AMD Infinity architecture with higher speed 'Zen 2' cores for optimal performance on database, commercial High Performance Computing (HPC) and hyperconverged infrastructure workloads.

Aldec has enhanced its unified requirements lifecycle management EDA tool, Spec-TRACER, to support the exchange of system and hardware data with IBM Requirements Engineering DOORS Next product, commonly used by system engineers.

Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).

It has been announced by imec that the IEEE Std 1838TM-2019, recently approved by the IEEE Standards Association, will be included in IEEE Xplore Digital Library from February 2020 onward. The new standard allows die makers to design dies which, if compliant to this standard, constitute, once stacked in a 3D-IC by a stack integrator, a consistent stack-level test access architecture.

SureCore is opening its low power memory compiler for 30 days to qualifying companies to evaluate the capabilities of its PowerMiser and EverOn standard SRAM IP products on low power metrics. The new service will prove particularly useful for constraint and compute intensive SoC designs.

Digi-Key Electronics is ready to roll into embedded world 2020 in Nuremberg (February 25-27) with a comprehensive menu of interactive technical demonstrations, traditional games and giveaways. The company is also an official sponsor of Student Day on February 27, when 1,000 final-year engineering students from around the world gather to meet potential employers.