Search results for "EDA"

Rohde & Schwarz and Cadence have collaborated on a solution aimed at simplifying the engineering process from RF design to implementation and enhancing accuracy by using realistic signals for both simulation and testing.

The Spirent Chip Design Verification Solution speeds up the entire silicon development lifecycle and delivers significant cost savings by identifying and addressing issues in the IC design phase and before manufacturing starts. Combining network testing technology from the leading Ethernet test company with an industry-leading emulation system provides more accurate and faster verification for Ethernet SoCs.

Avishtech, a provider of innovative EDA stack-up and 2D field solver solutions, has joined Altium’s Nexar partner ecosystem. Avishtech joins a growing list of Nexar partner organisations, including Arduino, Arrow, Diotech, Keysight Technologies, Microchip, Samtec, and Ultra Librarian.

Cadence Design Systems has announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals.

X-FAB Silicon Foundries has announced the release of a reference design kit for Tanner analogue/mixed-signal (AMS) software from the EDA segment of Siemens Digital Industries Software. The new kit is based on silicon-proven circuitry, providing full coverage of the flow to design and simulate analogue and mixed-signal ICs.

Imperas Software has announced that SiFive has qualified the Imperas models for the full range of the SiFive processor Core IP Portfolio. Simulation models are an essential starting point for early SoC architectural exploration, as system designers use virtual platforms to test full application workloads and datasets to optimise multicore configurations.

Advantest is pilot testing a next-generation solution for performing both high-speed scan testing and software-driven functional device testing on its V93000 platform by leveraging the existing high-speed serial I/O interfaces on advanced integrated circuits (ICs).

Aldec has launched HES-DVM Proto Cloud Edition (CE). Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and has a focus on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.

Cadence Design Systems has announced that JVCKENWOOD has adopted the new Spectre FX Simulator and multiple Cadence custom, analogue, digital and verification solutions to accelerate IC development of its consumer electronics applications while minimising overall design risk.

Jeroen Leinders, Global eCADSTAR Solutions Leader and Chris Hambleton, General Manager, Zuken, address the pain points in schematic and PCB design.