Synopsys has announced that Kyocera Document Solutions has achieved first-pass silicon success for its new multifunction product (MFP) SoC using Synopsys DesignWare ARC EV6x Embedded Vision Processor IP with convolutional neural network (CNN) engine and ARC MetaWare EV Development Toolkit.

Synopsys has announced that Sondrel has adopted the Synopsys Fusion Design and Verification Continuum platforms to accelerate the design and verification of large, complex system-on-chip (SoC) designs for automotive, AI, machine learning, IoT, consumer AR/VR gaming, and security applications. Sondrel plans to use solutions from Synopsys' design and verification platforms to create power-efficient designs for their customers.

Synopsys has announced the release of version 9.1 of its LightTools illumination design software, which expands LightTools' features and workflows for illumination optics design with new tools to model and analyse light detection and ranging (LiDAR), AR/VR, and biomedical systems.

Synopsys has announced that it has been recognised as a leader in The Forrester Wave: Static Application Security Testing, Q1 2021. The report identifies the 12 most significant vendors in the static application security testing (SAST) market and evaluates them against 28 criteria in three high-level categories: current offering, strategy, and market presence.

Synopsys has announced that AImotive has adopted Synopsys VCS simulation and Verdi debug, part of the Verification Continuum Platform, to help verify its innovative aiWare hardware IP for Neural Network (NN) acceleration for automated driving applications.

Synopsys has announced its collaboration with Samsung Foundry to deliver a new certified digital implementation, timing and physical signoff reference flow accelerating high-performance compute designs using the Synopsys Fusion Design Platform.

Synopsys has announced the availability of the Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for performance in data-intensive system-on-chips (SoCs). 

Synopsys and Samsung Foundry has announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving and advanced driver-assistance systems (ADAS) applications.

Synopsys has announced its collaboration with SiMa.ai to bring its machine learning inference at scale to the embedded edge. Through this engagement, SiMa.ai has adopted key products from Synopsys DesignWare IP, Verification Continuum Platform, and Fusion Design Platform for the development of their MLSoC, a purpose-built machine-learning platform targeted at specialised computer vision applications, such as autonomous driving, surveillance, and ...

Synopsys has announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package.

Synopsys has announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids).

Synopsys has announced that Graphcore achieved first-pass silicon success using an IC Compiler II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on a 7nm advanced process technology.

Synopsys has unveiled its Silicon Lifecycle Management (SLM) platform, a data-analytics-driven approach to optimising SoCs from the design phase through to end-user deployment. The SLM platform, which is tightly coupled with Synopsys' market-leading Fusion Design Platform, will provide visibility into critical performance, reliability and security issues for the entirety of a chip's lifespan.

Synopsys has announced that Shankar Krishnamoorthy has been promoted to GM of the Digital Design Group. Krishnamoorthy, who rejoined Synopsys in 2017, is an electronic design automation veteran with 25 years of experience bringing to market high-value, market-leading physical design and logic synthesis solutions.

Synopsys has announced that its DesignWare CXL Controller IP now supports the AMBA CXS protocol, enabling an efficient interface with the latest, highly scalable Arm Neoverse Coherent Mesh Network to provide an optimised multichip IP stack for a range of high-performance computing, datacenter, and networking system-on-chip (SoCs). 

Synopsys has announced that NSITEXE adopted Synopsys HAPS-80 prototyping solution to develop their current and next-generation Data Flow Processor (DFP) IP portfolio. HAPS-80 delivers the high-performance needed for software development and system validation of NSITEXE's RISC-V based accelerator with a complex 512-bit vector processing unit for vehicle control microcomputers.

Synopsys has announced that Sassine Ghazi has been appointed as Chief Operating Officer. Ghazi, who joined Synopsys in 1998, brings multiple decades of experience in chip design, applications engineering, customer support, sales, and business management.

Synopsys has announced that JLQ Technology has selected Synopsys DesignWare Interface IP to accelerate development of its new generation of high-performance, low-power systems-on-chips (SoCs) for a range of applications.

Synopsys has announced that the Defense Advanced Research Projects Agency (DARPA) has selected Synopsys as a prime contractor for the Automatic Implementation of Secure Silicon AISS program. The program's goal is to automate the inclusion of scalable hardware security mechanisms in IP and system-on-chips (SoCs) to explore security versus other design trade-offs.

Synopsys has announced that its collaboration with TSMC and Microsoft has delivered a highly scalable timing signoff flow for use in the cloud. This extensive, multi-month collaboration among the three industry partners speeds up the path to signoff next-generation systems-on-chips (SoCs).