Cadence Design Systems and ArcSoft has announced they have partnered to develop AI and vision applications for Cadence Tensilica Vision DSPs. ArcSoft has collaborated with Cadence to port beauty shot, high dynamic range (HDR), bokeh and facial unlock applications to the Vision P6 DSP. The joint solution has been designed into an applications processor from a global provider and is now shipping in smartphones.

Cadence Design Systems has announced that its Cadence Automotive Solution has been used by ROHM for safety verification, a critical component of its ISO 26262-compliant tool chain for automotive LSIs. The ROHM flow, which has achieved ASIL D certification from TÜV Rheinland, which utilises Cadence fault injection simulation technology, and can reduce the effort required to complete the safety verification process by up to 50% for automo...

It has been announced by Cadence Design Systems, that Hitachi has used the Cadence JasperGold Formal Verification Platform to developνCOSS S-zero, an industrial facilities functional safety controller that has been certified for Safety Integrity Level (SIL) 3 in accordance with the International Electrotechnical Commission (IEC) 61508 Series functional safety standard.

Cadence Design Systems has announced that its full-flow digital and signoff tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (LPP) process technology. The Cadence tools were certified for the Process Design Kit (PDK) and foundation library on the 7LPP process and confirmed to meet Samsung Foundry’s accuracy requirements, enabling systems and semiconductor companies to accelerate the delivery of 7LPP desi...

It has been announced by Cadence Design Systems, that the Cadence Perspec System Verifier supports the new Accellera Portable Test and Stimulus Specification (PSS) 1.0 released by the Accellera Systems Initiative. The Accellera PSS enables a single representation of System on Chip (SoC) tests and coverage metrics for hardware and software verification, creating efficiencies for design engineers.

A broad cloud portfolio for the development of electronic systems and semiconductors, Cadence Cloud portfolio, has been launched by Cadence Design Systems. The Cadence Cloud portfolio consists of Cadence managed and customer managed environments that enable electronic product developers to use the scalability of the cloud to securely manage the increase in design complexity.

A software product that meets the challenges of designing high reliability analogue and mixed-signal Integrated Circuits (ICs) for automotive, medical, industrial, and aerospace and defence applications has been introduced by Cadence Design Systems. The product is called the Legato Reliability Solution which provides analogue designers with the tools they need to manage their design’s reliability throughout the product life c...

Cadence Design Systems has announced that Cadence Sigrity PowerDC technology supports Future Facilities’ new open neutral file format, which solves the challenge of sharing design models between different thermal simulation toolsets. The PowerDC technology’s adoption of the single, open-model file format streamlines the thermal supply chain, promotes interoperability and data exchange, and enables customers to improve their thermal an...

  Research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems has announced that its extensive, long standing collaboration has resulted in the industry’s first 3nm test chip tapeout.

Cadence Design Systems has announced that GEO Semiconductor selected the Cadence Tensilica Vision P5 DSP for GEO’s new GW5400 camera video processor. According to GEO, their GW5400 is the world’s first automotive smart viewing processor.

  Developer of multi-system Global Navigation Satellite System (GNSS) products, Galileo Satellite Navigation (GSN), and Cadence Design Systems have announced that the software-based GNSS global positioning system (GPS) receiver from GSN is now available for the Cadence Tensilica Fusion F1 DSP.

At embedded world 2018 Cadence Design Systems will showcase its latest Cadence Tensilica DSPs and design tools targeted for automotive applications. The demonstrations will take place in hall 4/4-116 at the Exhibition Centre in Nuremberg, Germany from 26th February to 1st March 2018, where the theme of the event is 'Automotive Electronics Redefined'.

In order to address the challenges of designing and verifying Fan-Out Chip-on-substrate (FOCos) multi-die packages, Advanced Semiconductor Engineering and Cadence Design Systems have collaborated to release a System-in-Package (SiP) EDA solution. The solution consists of the SiP-id (System-in-Package - intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodo...

Supposedly becoming the first DSP IP core to provide this capability, Cadence Design Systems has announced that its Tensilica HiFi DSP core now supports Dolby Atmos for PCs. Cadence has optimised Dolby Atmos to run on the HiFi DSP, enabling consumers to experience Dolby Atmos over headphones or through PC speakers while reducing power consumption and improving battery life. A number of PCs featuring Dolby Atmos are currently available, inclu...

Cadence Design Systems has announced Cadence Allegro Pulse, what it claims to be the PCB industry’s first solution to enable extended team collaboration by providing near real time insights into the complexities of the electronic design process. Allegro Pulse connects management, engineering, procurement and other business stakeholders to up-to-date work-in-progress design data in a single, unified web-based platform, enabling design teams ...

  The availability of what the company claims to be the industry’s first Verification IP (VIP) in support of the new PCI Express (PCIe) 5.0 architecture has been announced by Cadence Design Systems.

  Global fabless semiconductor and IC design company, HiSilicon, has selected the Cadence Tensilica Vision P6 DSP for its 10nm Kirin 970 mobile application processor, which debuted in Huawei’s new Mate 10 series mobile phones. In deploying the Vision P6 DSP, HiSilicon added valuable imaging and vision processing capabilities to the Kirin SoC.

Cadence Design Systems has announced that it has acquired nusemi inc, a company focused on the development of ultra-high-speed Serialiser/Deserialiser (SerDes) communications IP. SerDes solutions enable high-speed communications between chips, backplane and long-haul optical interconnect by converting between parallel data and extremely high-speed serial data streams with improved signal reliability.

Early access to the Cadence Xcelium Parallel Logic Simulation on Arm-based servers has been announced by Cadence Design Systems and Arm, providing what it supposedly a first-of-its-kind low-power, high-performance simulation solution for the electronics industry. Prior to manufacturing, verifying that SoC designs function correctly is a massive task accounting for over 70% of the EDA compute workload, and is a key driver for growth and trans...

Provider of system design tools, software, IP, and services, Cadence Design Systems, has announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for the GLOBALFOUNDRIES 22FDX process technology. The Cadence tools enable advanced-node customers across a variety of vertical markets - including automotive, mobile, IoT and consumer applications - to use GF’s fully depleted silic...