Cadence Design Systems has announced that Hiroshima University is using Cadence technology in its development of a computer-aided diagnosis system for colorectal endoscopic images. Led by Associate Professor Koide of the Research Institute for Nanodevice and Bio Systems (RNBS), the team developed the computer-aided diagnosis system using the Cadence Tensilica Vision P6 digital signal processor (DSP) core for convolutional neural network (CNN) pro...

In order to accelerate ASIC development for delivery of its automation equipment for test and industrial applications, Cadence Design Systems has announced that Teradyne has standardised its simulation tasks using the Xcelium Parallel Logic Simulator. With the Xcelium simulator, Teradyne achieved a two times performance speedup with production-use single-core, mixed-signal ASIC verification when compared with its previous simulation solution.

Cadence Design Systems has announced that it has achieved the industry’s first comprehensive 'Fit for Purpose - Tool Confidence Level 1 (TCL1)' certification from TÜV SÜD, enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive safety requirements. To achieve certification, Cadence provided its tool and flow documentation to TÜV SÜD for evaluation, and TÜV...

  In order to improve the development of its multi-functional printer SoCs, Fuji Xerox used Cadence Design Systems' Cadence Genus Synthesis Solution. The Cadence solution enabled Fuji Xerox to reduce its timing closure schedule more than 50% and achieve up to 16% area reduction for its sub-blocks, resulting in an eight percent total chip area reduction when compared with its previous solution.

Cadence Design Systems has announced that its set of Design for Manufacturing (DFM) tools are now qualified on Samsung Electronics’ 28nm FD-SOI/14nm/10nm process technologies. The Cadence DFM solutions have been updated to comply with Samsung Foundry’s mandatory 28nm FD-SOI/14nm/10nm process technology requirements, enabling customers to create complex, advanced-node designs for the automotive, mobile, Internet of Things (IoT), high-p...

Cadence Design Systems has announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development proce...

The full-flow digital and signoff tools from Cadence Design Systems and its custom/analogue tools have been certified/enabled for the Intel 22FFL (FinFET Low-Power) process, which provides up to 100 times lower leakage and a 2.5X active power reduction compared with its previous 22GP (general purpose) offering.

A solution to perform real time, in-design design-for-manufacturing (DFM) checks integrated with electrical, physical and spacing design rule checks (DRCs) has been introduced by Cadence Design Systems: Cadence Allegro PCB DesignTrue DFM technology. The new technology, integrated into the Allegro PCB Editor, enables PCB designers to identify and correct errors immediately, long before manufacturing signoff.

  Cadence Design Systems has announced that Cadence digital, signoff and custom/analogue tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for customers seeking to deploy 12FFC. In addition, Cadence IP is ready for design starts on the new 12FFC process.

In order to advance 7nm FinFET Plus design innovation for mobile and high-performance computing (HPC) platforms, Cadence Design Systems has announced its collaboration with TSMC. The Cadence digital, signoff and custom/analogue tools have achieved certification for the latest version of TSMC’s 7nm FinFET Plus process, and Cadence also delivered enhancements to the Cadence library characterisation flow.

A collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip with TSMC 7nm FinFET process technology for delivery in 2018 has been announced by Xilinx, Arm, Cadence Design Systems, and TSMC. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Arm CPUs working via a coherent fabric to off-chip FPGA accelerators.

A comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology has been delivered by Cadence Design Systems. This broad IP portfolio enables a host of applications ranging from in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems and is registered in the TSMC9000A programme.

An integrated solution for memory design and verification has been announced by Cadence Design Systems. The Legato Memory Solution eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to two times when compared with previous point tool offerings. The first-of-its-kind Legato Memory Solution’s cohesive design environment automates design steps and l...

  In order to support Arm Cortex-A75 and Cortex-A55 CPUs, based on Arm DynamIQ technology, and the Arm Mali-G72 GPU, the latest offerings from Arm for premium mobile, machine learning, and consumer devices, Cadence Design Systems has optimised its full-flow digital and signoff tools and the Cadence Verification Suite.

Targeted for the latest mobile and home entertainment applications, including smartphones, augmented reality (AR)/3D goggles, digital TVs and set-top boxes (STBs), Cadence Design Systems has announced the Cadence Tensilica HiFi 3z DSP IP core for system-on-chip (SoC) designs. The new HiFi 3z architecture offers more than 1.3 times better voice and audio processing performance than its predecessor, the HiFi 3 DSP.

In order to complete a successful ASIC design tapeout, Toshiba Electronic Devices & Storage used the Cadence Genus Synthesis Solution. The solution, used with the CPF-based low-power flow, enabled Toshiba to reduce logic synthesis runtime by two times versus its previous logic synthesis solution. Toshiba also experienced a 5.7% leakage power reduction for a standard cell portion during a trial evaluation of the Genus Synthesis Solut...

Cadence Design Systems has announced that the Cadence Functional Safety Verification Solution was adopted by ROHM CO in its design flow for ISO 26262-compliant ICs and LSIs for the automotive market. The Cadence fault simulation technology and seamless reuse of functional and mixed-signal verification environments enables an ISO 26262-compliant development flow that can reduce the effort required to complete the safety verification process up to ...

In order to port the AUTOSAR-compliant TOPPERS ATK2-SC1 (Toyohashi OPen Platform for Embedded Real-time Systems Automotive Kernel version-2 Scalability Class 1) to Cadence Tensilica processors and DSPs, Cadence Design Systems has collaborated with the embedded real time System Laboratory of Nagoya University. Nagoya University and Cadence jointly ported the ATK2-SC1 to the Tensilica processor platform, validating that it functions correctly and o...

Cadence Design Systems has announced that its custom/analogue and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES (GF) 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40% better performance and twice the area scaling than the previous 14nm FinFET technology.

Expanded support has been announced for Cadence Design Systems' enhanced ARM DesignStart programme, including the newly added ARM Cortex-M3 processor and the ARM CoreLink SDK-100 System Design Kit, which includes the fully verified CoreLink SSE-050 subsystem, enabling engineers to further accelerate the delivery of mixed-signal Internet of Things (IoT) designs.