The availability of the industry’s first Verification IP (VIP) in support of the recently announced USB4 standard has been announced by Cadence Design Systems. The Cadence VIP for USB4 enables engineers to develop standard-compliant system-on-chip (SoC) designs, completing functional verification of the design with less effort and greater assurance that the SoC will operate as expected.

Cadence Design Systems announced that Toshiba Memory Corporation has successfully used the Cadence CMP Process Optimiser, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7% accuracy to silicon.

Early availability of the complete, silicon-proven Cadence Denali Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology has been announced by Cadence Design Systems. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications.

Products in the Cadence Tensilica functional safety portfolio and its design processes have achieved certification of ISO 26262 compliance up to ASIL D for the development of automotive applications. The Tensilica products and processors offer the broadest range of ISO 26262-compliant processors and DSPs and continue to expand across vision, AI, radar, lidar, sensor fusion, wireless/wired communication, audio/voice processing and highly optimised...

Boosting performance by up to 10X for Automotive Radar/Lidar and up to 30X for 5G communications the Cadence Tensilica ConnX B20 DSP IP becomes the highest-performing DSP in the ConnX family. Based on a deeper processor pipeline architecture, this DSP provides a faster and more power-efficient solution for the automotive and 5G communications markets, including next-generation radar, lidar, vehicle-to-everything (V2X), user equipment (UE)/infrast...

It has been announced that Cadence Design Systems and Green Hills Software, have entered into a strategic partnership that is expected to drive embedded system safety and security. As part of the partnership, Cadence has invested about $150 million that represents an approximate 16% ownership interest in Green Hills, and Cadence CEO, Lip-Bu Tan, has joined the Green Hills Board of Directors.

It has been announced that GLOBALFOUNDRIES (GF), has chosen Cadence Design Systems as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has reportedly come to rely on the features, capacity, speed and scalability of the Cadence digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows.

It has been announced by Cadence Design Systems that MaxLinear has used Cadence timing signoff tools to successfully deliver the MxL935xx Telluride device, a 400Gbps PAM4 system on chip (SoC) using 16FF process technology. The Cadence Quantus Extraction Solution and Tempus Timing Signoff Solution were key enablers of the on-time delivery of working silicon for MaxLinear.

Cadence Design Systems, has unveiled the industry’s first silicon-proven, long-reach 112G SerDes IP in seven nanometre. The Cadence seven nanometre 112G PAM-4 SerDes IP delivers industry-leading power, performance and area (PPA) efficiency required to build high-port density networking products for next-generation cloud-scale and telco datacenters. 

Cadence Design Systems Cloud-Hosted Design Solution has undergone rigorous technical validation and achieved Amazon Web Services Industrial Software Competency status. This recognizes the Cadence solution has demonstrated technical proficiency and proven customer success with electronic systems and semiconductor companies. The Cadence Cloud-Hosted Design Solution enables customers to increase the pace of product innovation while decreasing produc...

Cadence announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing designs. As part of the collaboration, the Cadence digital, signoff and custom/analog tools have achieved the latest Design Rule Manual and SPICE certification for the TSMC 5nm and 7nm+ processes, and the corresponding process design kits are now available for download....

A collaboration between Cadence Design Systems and Arm has been announced to enable high-performance computing (HPC) customers to execute bare metal pre-silicon verification compliance tests through the Arm Server Base System Architecture (SBSA) Compliance Suite.

It has been announced by Cadence Design Systems, that the Cadence Verification Suite is now enabled for Arm-based high-performance computing (HPC) server environments. Through an industry ecosystem collaboration, software tools in the suite, include Xcelium Parallel Logic Simulation, and run on the Hewlett Packard Enterprise (HPE) Apollo 70 System.

Cadence announce the Cadence Tensilica DNA 100 Processor IP, the first deep neural-network accelerator AI processor IP to deliver both high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. As a result, the DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles, ADAS, surveillance, robotics, drones, augmented reality /virtual reality...

  The collaboration between Cadence Design Systems, and TSMC is set to continue, in order to certify Cadence’s design solutions for TSMC five nanometre and seven nanometre+ FinFET process technologies for mobile and high-performance computing (HPC) designs.

The Cadence Tensilica DNA 100 Processor IP, deep neural-network accelerator (DNA) AI processor IP delivers high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. As a result, the DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR) /virtual reality (VR), smartphone...

Cadence Design Systems has announced that it has launched a broad ecosystem with nine initial PCB manufacturing partners to enable customers to easily get the partners’ technology files they need to ensure PCB design manufacturability early in the design process. This reduces rework, shortens design cycles, and accelerates new product introduction.

It has been announced by Cadence Design Systems that its full-flow digital tool suite has achieved certification for the GLOBALFOUNDRIES (GF) 22FDX process technology. The GF certification process was completed using the Cadence Tensilica Fusion F1 DSP, which targets Internet of Things (IoT) and wearables applications.

Cadence Design Systems has announced that Global Unichip Corporation (GUC) has adopted the Cadence Palladium Z1 Enterprise Emulation Platform to accelerate system-on-chip (SoC) design and drive innovation in the semiconductor industry.

Cadence Design Systems has announced its Cadence Sigrity 2018 release, which includes new 3D capabilities that enable PCB design teams to accelerate design cycles while optimising cost and performance. A 3D design and 3D analysis environment integrating Sigrity tools with Cadence Allegro technology provides a more efficient and less error-prone solution than current alternatives utilising third-party modeling tools, saving days of ...