Cadence unveil that Fujitsu has decreased the regression verification time for a system-on-chip design by 3X using the Incisive Enterprise Simulator and the Incisive Enterprise Manager. Part of the Cadence System Development Suite, the Incisive functional verification platform delivers unique verification management and automation capabilities that tackle the complexities of SoC verification.

Cadence Design Systems unveil that Ricoh have chosen the Cadence Palladium XP verification computing platform for its multifunction printer system-on-chip development, after an extensive competitive benchmarking process. Achieving the fastest design “bring-up” compared to alternative solutions, the Palladium XP platform with Cadence PCIe 2.0 Accelerated Verification IP also delivered a 40X verification speed-up over RTL logic simulation.

Cadence Design Systems announce a groundbreaking approach to custom design with its Virtuoso Layout Suite for Electrically Aware Design. Offering increased design team productivity and circuit performance for custom ICs, Virtuoso Layout Suite EAD allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance.

Cadence Design Systems announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own cutting-edge IP. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers, creating and delivering fully qualified and high-quality native SKILL-based PDKs to enable all the leading-edge features of the Virtuoso platform.

Addressing the design challenge of reducing energy consumption of power-hungry datacenters and enterprise applications, Cadence Design Systems, today announced new design IP for low-power PCI Express development.

Cadence Design Systems today announced that it has completed the acquisition of the IP business of Poland-based Evatronix. The acquisition further strenthens Cadence Design Systems' IP cores portfolio.

Cadence Design Systems announced today that PMC has adopted the Cadence Physical Verification System as signoff technology for its global design centers. PMC has used the Physical Verification System for several successful tapeouts, including PMC’s DIGI 120, described as the industry’s only single-chip processor supporting 10G, 40G and 100G speeds for OTN transport, aggregation and switching.

Cadence Design Systems announced today that several of its system-on-chip development tools have achieved version 0.1 of design rule manual and SPICE model tool certification for TSMC’s 16-nanometer FinFET process.

Cadence Design Systems announced today that TSMC has certified the new Cadence Tempus Timing Signoff Solution at 20 nanometers. The certification means the Cadence Tempus Timing Signoff Solution passes TSMC’s rigorous EDA tool certification to enable customers to achieve accuracy required for advanced technologies.

In a move to ease and speed the development of complex ICs, Cadence Design Systems introduce the Tempus Timing Signoff Solution, a new static timing analysis and closure tool designed to enable System-on-Chip developers to speed timing closure and move chip designs to fabrication quickly. The Tempus Timing Signoff Solution represents a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for fa...

Cadence Design Systems today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs.

Cadence Design Systems today announced its intent to acquire the IP business of Evatronix SA SKA, adding to its rapidly expanding IP offering. Based in Poland, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, Display, MIPI, and storage controllers, which are highly complementary to Cadence’s IP offering.

Cadence Design Systems today introduced a new version of Incisive Enterprise Simulator, with features that improve low-power verification productivity of complex SoCs by thirty percent. The 13.1 release of Cadence Incisive Enterprise Simulator addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification for today’s most complex SoCs.

Cadence Design Systems announced that GLOBALFOUNDRIES has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20 and 14 nanometers. GLOBALFOUNDRIES is using the Cadence Pattern Classification and Pattern Matching Solutions because they enable up to four times faster design for manufacturing, which is key to improving customers’ silicon yield and predictability.

Cadence Design Systems today announced results for the first quarter of fiscal year 2013. Cadence reported first quarter 2013 revenue of $354 million, compared to revenue of $316 million reported for the same period in 2012.

Cadence Design Systems announce an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs – from design analysis through signoff – and will deliver the infrast...

Fulfilling the promise of performance and power scaling at 16 nanometers, ARM and Cadence today announced details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16-nanometer FinFET manufacturing process.

Cadence Design Systems today announced that it has entered into a definitive agreement to acquire Tensilica for approximately $380 million in cash. Tensilica had approximately $30 million of cash as of December 31, 2012.

Cadence Design Systems today introduced the first commercially available design IP (IP) and verification IP (VIP) supporting the new Mobile PCI Express (M-PCIe) specification, which enables today’s leading innovators to develop products with both PC-class performance and extended battery life.

Cadence Design Systems kicks off its worldwide series of user conferences, starting with CDNLive Silicon Valley, March 12 and 13 in Santa Clara. CDNLive conferences provide an excellent opportunity for Cadence customers to collaborate and dig deeper into the latest technologies and methodologies with Cadence experts.