Cadence Design Systems today announced its participation at DVCon 2013, the seminal conference for functional design and verification that takes place at the DoubleTree Hotel in San Jose, California on the 25-28 February 2013,

Cadence Design Systems today revealed the election of Young K. Sohn, president and chief strategy officer of Samsung Electronics to its board of directors. Mr. Sohn brings substantial industry, financial, operational and governance expertise to Cadence through his experience in executive leadership at leading semiconductor firms and advisory roles in investment firms. The company also announced the retirement of Donald L. Lucas from the board.

Cadence Design Systems today announced an agreement to acquire Cosmic Circuits Private Limited. Cosmic Circuits offers silicon-proven IP solutions in connectivity and advanced mixed-signal technologies in the 40nm and 28nm process nodes, with 20nm and FinFET development well underway.

Cadence Design Systems announced today that two of its major foundry partners—Samsung Foundry and GLOBALFOUNDRIES—are supporting new Cadence custom/analog technology targeting designs at the advanced nodes of 20 and 14 nanometers. The two foundries are providing SKILL-based process design kits for the newly introduced Cadence Virtuoso Advanced Node.

Cadence Design Systems announced today that GLOBALFOUNDRIES has certified essential Cadence technologies for custom/analog, digital and mixed-signal design, implementation, and verification for its 20-nanometer LPM technology. The certification covers the Virtuoso and Encounter platforms, including the industry-standard SKILL process design kit (PDK).

Cadence will introduce its joint development of advanced design technologies in partnership with the Common Platform Alliance (Samsung Electronics, IBM, and GLOBALFOUNDRIES) at the Common Platform Technology Forum on Feb. 5.

Cadence Design Systems has today announced production-proven verification IP for the new USB SuperSpeed Inter-Chip specification, enabling customers to thoroughly verify designs deploying the latest extension of the USB 3.0 protocol. The SSIC specification combines the MIPI Alliance physical interface with the upper layers of the USB protocol to enable USB 3.0 to connect chips within a mobile device.

Cadence Design Systems today announced the availability of Virtuoso Advanced Node, a new set of breakthrough custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below.

Cadence Design Systems announced that Avago Technologies used Cadence Encounter Digital Implementation (EDI) System to accelerate the design schedule and boost engineering productivity on a large-scale 28-nanometer networking chip. Avago achieved performance of 1GHz, a 57 percent improvement compared to the previous software.

Cadence Design Systems introduced a new version of its leading functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release. Incisive 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today’s complex int...

Cadence Design Systems have today announced its participation at embedded world 2013 to demonstrate the company’s latest innovations of its Cadence System Development Suite. Visitors to Cadence’s booth will have the opportunity to learn about the latest enhancements to the Cadence System Development Suite presented at this year’s annual Cadence user conference CDNLive EMEA in Munich, Germany.

Cadence Design Systems, Inc today announced the immediate availability of the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The standards-based Design IP and VIP support the latest Automotive Ethernet extensions as defined by the OPEN Alliance Special Interest Group (SIG). Together, both IP help speed today’s newest automotive requirements to market, including improvem...

Cadence Design Systems announced today that Renesas Micro Systems has adopted the Cadence Encounter RTL Compiler for synthesis, highlighting a utilization improvement of 15 percent, area reduction of 8.4 percent, quick turnaround time, and cost reduction for complex ASIC designs.

Cadence have announced that Open-Silicon has leveraged the latest innovations from the Cadence Encounter RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nanometer hardening of an ARM dual-core Cortex -A9 processor.

Cadence Design Systems announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM’s FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.

Cadence Design Systems today announced multiple successful verification projects using Cadence Verification IP for ARM AMBA protocols, one of the industry’s most widely used verification solutions for the AMBA protocol family.

Cadence reported third quarter 2012 revenue of $339 million, compared to revenue of $292 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $59 million, or $0.21 per share on a diluted basis, including $15 million in acquisition-related income tax benefit, in the third quarter of 2012, compared to net income of $28 million, or $0.10 per share on a diluted basis in the same period in 2011.

Cadence have unveiled enhancements to its Allegro 16.6 Package Designer and System-in-Package Layout solution that support low-profile IC package requirements for next-generation smartphones, tablets, and ultra-thin notebook PCs. New features in Allegro 16.6 Package Designer and Cadence SiP Layout include open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package capabilit...

Cadence Design Systems announced today that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms. The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.

Cadence Design Systems announced today that TSMC has validated Cadence 3D-IC technology for its CoWoS (chip-on-wafer-on-substrate) Reference Flow with the development of a CoWoS test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP.